Re: [PEDA] bug?

2004-07-22 Thread bob stephens
Thanks Mike - and Colby. That solved the design rules not being saved
problem. Still have the overwritten text issue though.

Bob

-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED] 
Sent: Thursday, July 22, 2004 11:10 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] bug?

Bob

So far this answer worked for me when 2004 started to act funneee.
Delete the folder C:\Documents and Settings\yourname\Application
Data\Altium.  Then start 2004 again.  Colby at Tech support at Altium
steered me this way.  Colby is a great asset to Altium

Mike Reagan



-Original Message-
From: bob stephens [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 9:40 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] bug?


OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words "minimum clearance".

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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Re: [PEDA] bug?

2004-07-22 Thread Mike Reagan
Bob

So far this answer worked for me when 2004 started to act funneee.
Delete the folder C:\Documents and Settings\yourname\Application
Data\Altium.  Then start 2004 again.  Colby at Tech support at Altium
steered me this way.  Colby is a great asset to Altium

Mike Reagan



-Original Message-
From: bob stephens [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 9:40 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] bug?


OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words "minimum clearance".

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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[PEDA] bug?

2004-07-22 Thread bob stephens
OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words "minimum clearance".

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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Re: [PEDA] Bug / Buglet

2002-09-27 Thread Dwight

I recall some option that can be set to "include single-pin nets" -- this
might give you net-names for all those unconnected pins, then the usual
'update primitives from connected copper' (or whatever) would take care of
this.  I can't readily test this right now, but maybe it's enough to help...

> -Original Message-
> From: JaMi Smith [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, September 26, 2002 8:21 PM
>

> I have two 192 pin BGA's, one 957 pin BGA, and twelve 24 pin BGA's, on
which
> ALL pads go to a "via", with the exception of those that are directly
> connected to on the top side of the board by a trace that goes somewhere
> else.
>
> Since this board is somewhat of a "proto" board which is being used to
prove
> out the operation of some 1 GHz ADC's and a big Xilink FPGA operating at
500
> MHz, I have assumed that any of the pins might be required to be accessed
at
> any time, to add, change, or fix something, and as a result, I have
> intentionally left all of the vias attached and in the design, even though
> they are not in the schematic or netlist. This results in these items
being
> listed as an error in the DRC. This is a major annoyance, and I wish there
> was some way of eliminating these from the DRC, but since they do not have
a
> net name (they are all "No Net", they are kind of hard to assign to a
class
> and say ignore)...

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Re: [PEDA] Bug / Buglet

2002-09-26 Thread Tony Karavidas



> -Original Message-
> From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] 
> Sent: Thursday, September 26, 2002 9:28 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Bug / Buglet
> 
> 
> the windows task manager is not as smart as you or i would 
> like it to be
> 
> sometimes the 'not responding' is correct and it really is 
> all over and sometimes it is not correct and a process is 
> just taking a while 
> 
> i wouldn't be too eager to do the 3 finger salute
> 
> i recently had several 'crashes' (task manager not 
> responding) when doing a select inside operation i went 
> through the kill operation, sometimes reboot etc.
> 
> i finally tracked it down to a stupid logo on the board which 
> had a bazillion fills on the silkscreen the select inside 
> just didn't like that, even though it wasn't analyzing copper 
> i deleted the logo and all was fine and i'll just put it back 
> at the end
> 
> sometimes the online DRC or the netlist load lights up 
> problems that are not for real, just cancel, reset drc 
> markers and that trust what you have done is correct for the 
> moment and run a real DRC at the appropriate time later when 
> you have reviewed the situation and corrected real problems if any
> 
> i too have had many frustrating iterations of load the nets, 
> clear the nets, learn the traces, load the nets, but in 
> retrospect it seems that many times i was just trying too hard
> 
> it's not a perfect world but i have found that the 'real' RUN 
> DRC is very accurate 

Except for broken nets that are contained within a split plane
definition. I should check to  see if that got fixed in DXP.


 
> the poured polygons can be troublesome in this regard but 
> they actually work better than the software would sometimes 
> lead you to believe
> 
> as to your connector DRC errors from what i read they sound 
> real or possibly need a rule to be created 
> or your dual footprint may need a dual schematic object to 
> correspond correctly
> 
> i think deleting the pours is a mistake as a solution as it 
> compounds the errors as you have noted
> 
> you don't need to pre-edit the vias with the net name just 
> paste no net vias onto netted names and they will acquire the 
> right net, even a string of no net vias pasted onto various 
> nets will get the various nets independently 

Once Jami removed the poly, those vias somehow lost their netnames. I
could see how they would not have any netnames in the first place IF he
has placed them before the poly, but after the poly was deleted, it
baffles me as to why the vias didn't keep their nets.

Anyway, if those vias don't have netnames, any following poly pour would
not attach to them and he is stuck using 99SE. If Jami tried DXP, he
could use a query  (ObjectKind = 'Via') And (Net = 'No Net'). Oh, of
course, do the same thing in 99SE with global editing: Jami why not
select one of those no-net stitched vias and use the regular global
selection to select all vias that are not assigned to a net? Once you
have them selected, assign them to the net name of choice? If there are
mutiple regions, keep selecting all of them and deselecting the ones
outside of a given area. 

I think one thing you could try is to put a temporary keepout on the
poly layer under the TCXO and then you could have repoured the poly to
get out from under the TCXO and kept all your vias intact. Then you
could replace the TCXO and grab net from attached, then remove the
keepout and repour the poly.

Yeah, I don't do my polys until the very end, as you discovered.
 

> as to 26 splits ...
> i am far from an expert in this area but that sounds pretty 
> extreme a designer much smarter than i with whom i have 
> worked recently assured me 
> that in the end there really is only one ground and if 
> necessary you control circulating 
> currents and potentially polluting currents by means of 
> 'cuts' in the plane as opposed to full splits in the plane
> 
> these cuts are simply traces (non copper) on the plane in the 
> proper spots and have the effect of localizing the current 
> flows if applied properly
> 
> high speed traces should not cross either the cuts or splits 
> as is well known EMI issue
> 
> i have had problems with copying the database file, be 
> careful with that as it seems to refer to files in the 
> original database, in particular loaded netlists
> 
> if you are compelled to make a fresh start make a new empty 
> database file and drag files into that
> 
> Dennis Saputelli
> 
> 
> JaMi Smith wrote:
> > 
> > While there is a chance that we can chalk some or all of 
> this off to 
> > "operator s

Re: [PEDA] Bug / Buglet

2002-09-26 Thread Dennis Saputelli

the windows task manager is not as smart as you or i would like it to be

sometimes the 'not responding' is correct and it really is all over and
sometimes it is not correct and a process is just taking a while 

i wouldn't be too eager to do the 3 finger salute

i recently had several 'crashes' (task manager not responding) when
doing a select inside operation
i went through the kill operation, sometimes reboot etc.

i finally tracked it down to a stupid logo on the board which had a
bazillion fills on the silkscreen
the select inside just didn't like that, even though it wasn't analyzing
copper
i deleted the logo and all was fine and i'll just put it back at the end

sometimes the online DRC or the netlist load lights up problems that are
not for real, just cancel, reset drc markers and that trust what you
have done is correct for the moment and run a real DRC at the
appropriate time later when you have reviewed the situation and
corrected real problems if any

i too have had many frustrating iterations of load the nets, clear the
nets, learn the traces, load the nets, but in retrospect it seems that
many times i was just trying too hard

it's not a perfect world but i have found that the 'real' RUN DRC is
very accurate 

the poured polygons can be troublesome in this regard but they actually
work better than the software would sometimes lead you to believe

as to your connector DRC errors from what i read they sound real or
possibly need a rule to be created 
or your dual footprint may need a dual schematic object to correspond
correctly

i think deleting the pours is a mistake as a solution as it compounds
the errors as you have noted

you don't need to pre-edit the vias with the net name just paste no net
vias onto netted names and they will acquire the right net, even a
string of no net vias pasted onto various nets will get the various nets
independently 

as to 26 splits ...
i am far from an expert in this area but that sounds pretty extreme
a designer much smarter than i with whom i have worked recently assured
me 
that in the end there really is only one ground and if necessary you
control circulating 
currents and potentially polluting currents by means of 'cuts' in the
plane as opposed to full splits in the plane

these cuts are simply traces (non copper) on the plane in the proper
spots and have the effect of localizing the current flows if applied
properly

high speed traces should not cross either the cuts or splits as is well
known EMI issue

i have had problems with copying the database file, be careful with that
as it seems to refer to files in the original database, in particular
loaded netlists

if you are compelled to make a fresh start make a new empty database
file and drag files into that

Dennis Saputelli


JaMi Smith wrote:
> 
> While there is a chance that we can chalk some or all of this off to
> "operator stupidity", here is one big problem, and a few related little
> ones.
> 
> I've got a 9.5 x 9.5 inch 6 layer board, with all 4 internal planes being
> power and ground (23 little split plane islands), and all of the circuitry
> routed on the 2 external layers.
> 
> Additionally, I have 6 "Polygon Planes" covering the top and bottom of the
> of the board, which "pour" around existing routing and "fill" the open
> areas, all going to relevant grounds.
> 
> I have spent an exhorbanent amount of time to add "stitching vias" in these
> polygon "ground" planes. where I would place a track on the top layer
> outside of the perimeter of the board, edit the track and assign it to net
> GND, and then select and copy a tented via of the proper size, and with the
> grid set to .250", use E P (edit paste) to put vias on the track at .250
> intervals, which, because I am using E P, would all correctly assume the net
> of the track that I was placing them on, GND. I would then select the entire
> line of vias, without the track, and copy them using E A (paste array)
> keeping the net name, on to the board, in rows, one  at a time, also spaced
> at .250", but checking each row as I proceed to delete any of these
> "stitching vias" that fall into the wrong area, or cause shorts, or other
> problems. Once I completed this process for one ground plane area, I would
> do a global edit on my "string of vias" outside the board and change the
> nets to GNDI, one of my analog grounds, and repeat the process in that area
> of the board.
> 
> Problem here is, that as I have been working on the board, the engineers at
> another company, for whom I am doing the board, are making some subtle
> changes. They do their schematics in OrCAD, but I only have an older version
> (7.2), so we are doing all changes by importing netlists, which has been
> working fine.
> 
> Very large Polygon Planes, especially when there mixed with large amounts of
> routing, or other "obstacles", appear to have the ability to bring Protel to
> its knees.
> 
> I learned this on faster machines now on 866 Mhz P3), where even with a

[PEDA] Bug / Buglet

2002-09-26 Thread JaMi Smith

While there is a chance that we can chalk some or all of this off to
"operator stupidity", here is one big problem, and a few related little
ones.

I've got a 9.5 x 9.5 inch 6 layer board, with all 4 internal planes being
power and ground (23 little split plane islands), and all of the circuitry
routed on the 2 external layers.

Additionally, I have 6 "Polygon Planes" covering the top and bottom of the
of the board, which "pour" around existing routing and "fill" the open
areas, all going to relevant grounds.

I have spent an exhorbanent amount of time to add "stitching vias" in these
polygon "ground" planes. where I would place a track on the top layer
outside of the perimeter of the board, edit the track and assign it to net
GND, and then select and copy a tented via of the proper size, and with the
grid set to .250", use E P (edit paste) to put vias on the track at .250
intervals, which, because I am using E P, would all correctly assume the net
of the track that I was placing them on, GND. I would then select the entire
line of vias, without the track, and copy them using E A (paste array)
keeping the net name, on to the board, in rows, one  at a time, also spaced
at .250", but checking each row as I proceed to delete any of these
"stitching vias" that fall into the wrong area, or cause shorts, or other
problems. Once I completed this process for one ground plane area, I would
do a global edit on my "string of vias" outside the board and change the
nets to GNDI, one of my analog grounds, and repeat the process in that area
of the board.

Problem here is, that as I have been working on the board, the engineers at
another company, for whom I am doing the board, are making some subtle
changes. They do their schematics in OrCAD, but I only have an older version
(7.2), so we are doing all changes by importing netlists, which has been
working fine.

Very large Polygon Planes, especially when there mixed with large amounts of
routing, or other "obstacles", appear to have the ability to bring Protel to
its knees.

I learned this on faster machines now on 866 Mhz P3), where even with a much
smaller board, and faster machine (2.2 GHz P4), it would take Protel up to
20 seconds to recover, "analyze GND", and redraw a screen from a simple
thing like deleting one of these "stitching vias", when Polygon Planes were
involved.

Anyway, I 've learned by this that I do not want to put the "Polygon Planes"
into the design until the last possible minute, because of the way that they
overload Protel.

Problem is that I have one Precision Oscillator (TXO) which has two possible
sources and two possible packages, and hence I have a "dual footprint", and
because of this, I have "copper" in the "component part" in PCB Lib, which
means I need to do an "Update Free Primitives From Component Pads", after
updating the board by importing a new netlist with changes.

This was no problem in doing this prior to adding the Polygon Planes to the
top and bottom layers.

Anyway, after adding the Polygon  Planes, I do an "Update Free Primitives .
. .", and it takes forever, and appears to have gone south, and I check with
"Task Manager", and it reports that Client99se is "Not Responding", so I
kill it and try again. This was the problem of repeated "crashes" that I had
a week or two back when I had DXP eat my backup file.

Anyway, I tried deleting the Polygon Planes on the outer layers, figuring I
can just take an extra 10 minutes and add them back in, and the "Update Free
Primitives . . . " works properly, and correctly updates the copper on the
TXO, but this time, since the polygon planes were not present, it lost the
net names of all of the hundreds of "stitching vias" that I added.

I can partially understand this, and almost accept it, since the vias are
copper, and not directly connected to a component pin, but they were in fact
directly connected to split planes that do in fact have defined net names.

I will call this Bug or Buglet number 2.

Bug or Buglet number 1, of course, is Protel going "south for the winter" on
the "Update Free Primitives . . ." in the first place.

Ok, so I have shipped the board, and convinced the engineers to ignore the
DRC Errors associated with the "connected copper" on the "dual footprint".
But now I want to find out what happened.

I make a copy of the database, load it in, and do an "Update Free Primitives
. . .", and just simply walk away. I come back in a half an hour, and it is
still sitting there, I hit "Close" on the "Netlist Manager" dialogue box,
and it just sits there, so I walk away again. I come back in another 10
minutes, and it cleared the dialogue box, so I look at the TXO footprint,
and it is updated. GREAT!

So I close the database, without saving it, and start over, and this is what
I found after another 7 or 8 tries:

1.) After Selecting "Update Free Primitives . . ." from the "Netlist Manager
Menu", and then answering Yes to the "Update . . ." question box, Protel
turns off the main

Re: [PEDA] BUG - keepout tracks included in width DRC

2002-09-16 Thread Brian Sherer

No, he always thought BIG...

see:http://olympicpc.com/quotes/dirksen_senator_everett.html

http://olympicpc.com/quotes/dirksen_senator_everett.html

At 08:50 PM 9/16/02 -0700, you wrote:
>he may be your senator but it was WAY before billions
>it was 'million'
>
>still it makes my point
>
>Dennis Saputelli
>

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Re: [PEDA] Bug fixes anyone?

2002-06-26 Thread Tony Karavidas

Well in THAT terminology there are none. There are thousands of users that
are using Protel for "its intended purpose."  That doesn't mean there aren't
bugs...there are lots of them. The thing is we either know ways to avoid
them or they are infrequent, or we just put up with them and keep bitching
about them. Protel did release 6 free service packs, whereas any other
company would have charged us maintenance to get the problems resolved. I
think we've had a pretty good deal with Protel so far.

Many of us are annoyed with their new ATS policy. It could easily leave us
feeling like we may or may not get fixes because 'they have our money' and
what the incentive now???

I hope that is not the case, but regardless, the new version is going to
have to come out of the chute with very few major bugs. If it has some they
sure as hell better get fixed faster under ATS. Now with ATS, there will be
a much higher expectation for feature updates and constant improvements.
There will have to be enough enhancement to the product every year to keep
people on ATS past the first year, the second year, etc.






> -Original Message-
> From: Thomas [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, June 25, 2002 8:23 PM
> To: Protel Data Forum (E-mail)
> Subject: [PEDA] Bug fixes anyone?
>
>
> Anyone care to elucidate on current 99SE bugs for Mr Rose?
>
> I have an overwhelming compulsion to send him the yahoo bug database.
>
> Hehe.
>
> Tom.
>
> -Original Message-
> From: Altium Sales [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 26 June 2002 1:16 PM
> To: Thomas
> Subject: Re: Last chance to buy Protel 99 SE and receive a free flat
> panel monitor
>
>
> Hello Thomas
>
> Price for Protel 99SE in Australia is $8795.  This is Australian
> dollars and
> includes GST.
>
> As to bugs:  Can you please advise me of the particular bugs that are
> preventing you from
> using the software for it's intended purpose?  I will endeavour to have
> these addressed
> to your satisfaction.
>
> There are no guarantees that Protel DXP will be any better or worse than
> Protel 99SE.   All
> software sales have a 30 day money back guarantee.  A free 30 day trial CD
> will also be
> available.
>
> Kind Regards
> Craig Rose
> Manager
> Australian Sales and Support Centre
>
> - Original Message -
> From: "Thomas" <[EMAIL PROTECTED]>
> To: "'Altium'" <[EMAIL PROTECTED]>
> Sent: Tuesday, June 18, 2002 5:26 PM
> Subject: RE: Last chance to buy Protel 99 SE and receive a free flat panel
> monitor
>
>
> > US$8,000 (or taking into account the current exchange rate:
> AU$16,000) is
> a
> > ridiculous amount of money to pay for software that is full of bugs and
> will
> > not be supported by any future service packs. What guarantee do I have
> that
> > DXP wont end up the same way? Wake up idiot.
> >
> >
> >
> >
> > > -Original Message-
> > > From: Altium [mailto:[EMAIL PROTECTED]]
> > > Sent: Tuesday, 18 June 2002 3:23 PM
> > > To: Thomas
> > > Subject: Last chance to buy Protel 99 SE and receive a free flat panel
> > > monitor
> > >
> > >
> > > Dear Tom,
> > >
> > > This is your last chance to get Protel 99 SE and receive a
> > > FREE Samsung 18" flat panel digital LCD monitor!*
> > >
> > > To take advantage of this offer you must make the move to
> > > Protel 99 SE or buy an additional Protel 99 SE license before
> > > June 28th, 2002.* Protel 99 SE will not be available for
> > > purchase once Protel DXP is released.
> > >
> > > In addition to the free monitor, you will automatically
> > > receive an upgrade to Protel DXP (a $2,195 upgrade value) as
> > > part of your free 12 months ATS membership supplied with your
> > > purchase. For current Protel 99 SE special offers visit
> > > http://www.altium.com/pricing/p99se_pricing.asp or call 1800 030 949.
> > >
> > > Protel DXP represents the most significant upgrade to the
> > > Protel product line since the move to the Windows platform.
> > > Protel DXP delivers a host of new and enhanced features to
> > > the design desktop, such as:
> > >
> > > - A new topological autorouter providing superb
> > > completion rates and finished route quality
> > > - A significantly enhanced 'Design Explorer' platform to
> > > provide a more responsive and tightly integrated design environment
> > > - Native support for multi-channel design and design
> > > variants allo

Re: [PEDA] Bug fixes anyone?

2002-06-26 Thread Thomas



> -Original Message-
> From: Terry Creer [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 26 June 2002 3:05 PM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] Bug fixes anyone?
> 
> 
> >*snip*
> >"There are no guarantees that Protel DXP will be any 
> >better or worse than Protel 99SE."
> >*snip*
> 
> Ok - this disturbs me a little bit, though... This line 
> coming from the
> sales and support centre?!?
> 
> Are they actually aware of the existing bugs?
> 
>

Yep.


* Tracking #: 660066DCD2071A4B9BC9E4AEF9FA2FE91A7FDEFC
*


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Re: [PEDA] Bug fixes anyone?

2002-06-26 Thread Ian Wilson

On 01:23 PM 26/06/2002 +1000, Thomas said:
>Anyone care to elucidate on current 99SE bugs for Mr Rose?
>
>I have an overwhelming compulsion to send him the yahoo bug database.
>
>Hehe.
>
>Tom.

You are welcome to send it to him but he know it exists and can find it 
himself.

The critical phrase is:
"As to bugs:  Can you please advise me of the particular bugs that are 
preventing you from using the software for it's intended purpose?"

Since the intended purpose is designing PCB from schematics it would seem 
that either a lot of us are living in dream land or the product does do 
that.  But if the intended purpose is to, say, render an accurate 3D view 
of a PCB then it doesn't do that.  I had reason to go through the bug 
database in some detail recently - few of the errors are critical and many 
of them are actually things that could be done better.

Does it live up to the details in the marketing documents?  At times I have 
considered going through all the public info and looking for stuff that is 
contrary to our consumer protection and trading laws but why bother.  Do 
you know what stopped me last time - the release of P99SE.

This whole thing is a grey area.  Yes there are certainly bugs and some of 
them do make you wonder about the reliability a little but many of us are 
pumping out designs daily.  It would be very very interesting to test this 
though.  Pick a bug and see if the new and improved lemon-fresh ATS can do 
anything for us. A recent purchaser of P99SE (so it is under ATS) would 
need to report a bug and then see if it gets fixed.  Is a fix in DXP 
acceptable - not for a company that has standardised on P99SE it is not.

One known bug that does have the potential to cause problems with some 
designs is this one:

Date:2001/04/05
Summary: PCB: Move-Selection and flipping layers can tracks and other 
entities to disappear
Details: PCB 99SE SP6: If the 'L' key is used to flip a large selection 
onto the other side of a PCB, once placed, the tracks, free surface pads 
and maybe other entities may not be displayed. Additionally, components may 
be placed in wildly incorrect positions.

Best of luck,
Ian Wilson




>-Original Message-
>From: Altium Sales [mailto:[EMAIL PROTECTED]]
>Sent: Wednesday, 26 June 2002 1:16 PM
>To: Thomas
>Subject: Re: Last chance to buy Protel 99 SE and receive a free flat
>panel monitor
>
>
>Hello Thomas
>
>Price for Protel 99SE in Australia is $8795.  This is Australian dollars and
>includes GST.
>
>As to bugs:  Can you please advise me of the particular bugs that are
>preventing you from
>using the software for it's intended purpose?  I will endeavour to have
>these addressed
>to your satisfaction.
>
>There are no guarantees that Protel DXP will be any better or worse than
>Protel 99SE.   All
>software sales have a 30 day money back guarantee.  A free 30 day trial CD
>will also be
>available.
>
>Kind Regards
>Craig Rose
>Manager
>Australian Sales and Support Centre
>
>- Original Message -
>From: "Thomas" <[EMAIL PROTECTED]>
>To: "'Altium'" <[EMAIL PROTECTED]>
>Sent: Tuesday, June 18, 2002 5:26 PM
>Subject: RE: Last chance to buy Protel 99 SE and receive a free flat panel
>monitor
>
>
> > US$8,000 (or taking into account the current exchange rate: AU$16,000) is
>a
> > ridiculous amount of money to pay for software that is full of bugs and
>will
> > not be supported by any future service packs. What guarantee do I have
>that
> > DXP wont end up the same way? Wake up idiot.
> >
> >
> >
> >
> > > -Original Message-
> > > From: Altium [mailto:[EMAIL PROTECTED]]
> > > Sent: Tuesday, 18 June 2002 3:23 PM
> > > To: Thomas
> > > Subject: Last chance to buy Protel 99 SE and receive a free flat panel
> > > monitor
> > >
> > >
> > > Dear Tom,
> > >
> > > This is your last chance to get Protel 99 SE and receive a
> > > FREE Samsung 18" flat panel digital LCD monitor!*
> > >
> > > To take advantage of this offer you must make the move to
> > > Protel 99 SE or buy an additional Protel 99 SE license before
> > > June 28th, 2002.* Protel 99 SE will not be available for
> > > purchase once Protel DXP is released.
> > >
> > > In addition to the free monitor, you will automatically
> > > receive an upgrade to Protel DXP (a $2,195 upgrade value) as
> > > part of your free 12 months ATS membership supplied with your
> > > purchase. For current Protel 99 SE special offers visit
> > > http://www.altium.com/pricing/p99se_pricing.asp or call 1800 030 949.
> > >
> > > Protel DXP represents the most significant upgrade to the
> > > Protel product line since the move to the Windows platform.
> > > Protel DXP delivers a host of new and enhanced features to
> > > the design desktop, such as:
> > >
> > > - A new topological autorouter providing superb
> > > completion rates and finished route quality
> > > - A significantly enhanced 'Design Explorer' platform to
> > > provide a more responsive and tightly integrated design environment
> > > - Native support for mul

Re: [PEDA] BUG ! Protel does not check that a sch file has changed !!!!!!!!

2002-04-28 Thread Ian Wilson

On 10:47 AM 25/04/2002 +0200, Schmitt Michael said:

>so now close the sch files by doing so on the tabbing pane (above the
>schematic sheet with the name of the current file inside) and select close
>document. now protel just closes this document without asking for saving it
>nor does it save the file with the changes from the update. reopen the
>schematic an the fields are as the were before the update ...

Yes, this bug does exist and Protel are aware of it. I noticed the same 
thing while writing the server mentioned below.  I emailed support and the 
response was that I should add and then delete a dummy component to mark 
the document as dirty.  I was doing this but thought there must be a better 
method.  Simply changing the attribute of a component using SDK functions 
does not mark the document as dirty.

I will add this as a bug to the bug database.


>that ist realy very bad, as the database update takes so much time even with
>600MHz. my design here takes about 50minutes and is not very big. (no it ist
>not the network).

There is a server that is faster (many time faster) than Protels DB import...
(http://www.considered.com.au/Protel01.htm look for the CSExtractFromExcel 
server).

This server does mark any sch sheets that are modified as dirty.

Ian Wilson


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[PEDA] BUG ! Protel does not check that a sch file has changed !!!!!!!!

2002-04-25 Thread Schmitt Michael

Protel99SE SP6 & Win98SE

open a ddb and open a project that is hierarchical. 

now Menue -> Tools -> Database Links and perform an update of the schematics
from an DB4 file. A report BOM shows that the partfields have been updated
(they were empty before the Update)

so now close the sch files by doing so on the tabbing pane (above the
schematic sheet with the name of the current file inside) and select close
document. now protel just closes this document without asking for saving it
nor does it save the file with the changes from the update. reopen the
schematic an the fields are as the were before the update ...

that ist realy very bad, as the database update takes so much time even with
600MHz. my design here takes about 50minutes and is not very big. (no it ist
not the network).

i have cross checked that with different designs on different installations.

Dipl.-Ing. (FH) Michael Schmitt
Baumer Ident GmbH
Entwicklung / Development Department
Hertzstr. 10
D-69469 Weinheim
Deutschland / Germany
Tel. +49 (0) 6201 9957 - 30
Fax. +49 (0) 6201 9957 - 99
E-Mail : [EMAIL PROTECTED]
Web: http://www.baumerident.com

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Re: [PEDA] bug in protel bom generation?

2002-04-12 Thread Considered Solutions

On 01:26 PM 12/04/2002 -0400, [EMAIL PROTECTED] said:
><..snip..>
>If you ask Ian Wilson he has a Consolidated Partlist Server which I
>commissioned last year, that works incredibly well I might add.
>This server is configurable and may well serve your purpose.
>Regards,

http://www.considered.com.au/Protel01.htm

Saves asking for it.

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Re: [PEDA] bug in protel bom generation?

2002-04-12 Thread lloyd . good

Tim and Brad,
The BOM generator in Protel only considers two fields when sorting, the Part
Type and the footprint. This has been a source of pain for me in the past,
as unless you indicate on the schematic in the part type there is a
difference (ie. 10K 1% vs 10K 5%) these parts will be grouped together as
one, whichever the sorter finds first.
If you ask Ian Wilson he has a Consolidated Partlist Server which I
commissioned last year, that works incredibly well I might add. 
This server is configurable and may well serve your purpose.
Regards,




   GE Energy Services
__

Lloyd Good
Development Digitization

Substation Automation Solutions
General Electric Canada, Inc.
2728 Hopewell Place N.E., Calgary, Alberta T1Y 7J7  CANADA
Tel: 403.214.4777,  Dialcomm: 8.498.4777,  Fax: 403.287.7946
Website: www.gepower.com/geharrisenergy/

NOTICE: The information contained in this e-mail is privileged, confidential
and intended solely for the use of the addressee named above. If the reader
of this e-mail is not the intended recipient, you are hereby notified that
any dissemination, distribution or copying of this e-mail is strictly
prohibited. If you have received this e-mail in error, please notify me
immediately by telephone (collect) at (1) 403.214.4400 and destroy this
e-mail as well as any copy. Thank you.



-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 12, 2002 10:56 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] bug in protel bom generation?


Tim,
the first source by which schematic symbols are consolidated is the
PartType field. I couldn't find any Protel documentation which defines the
criteria for consolidation in a BOM but I know it starts with the PartType
field. Don't you think that Protel could give the schematic BOM generation a
bit more then a brief paragraph description in either the online help or the
manual?

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.


> -Original Message-
> From: Tim Fifield [mailto:[EMAIL PROTECTED]]
> Sent: Friday, April 12, 2002 9:34 AM
> To: Protel EDA Form
> Subject: [PEDA] bug in protel bom generation?
> 
> 
> When we generate a BOM in Protel format in P99SE SP6 some parts get
> consolidated even though their libref and several attributes 
> are different.
> Does anybody know why this might be happening?
> 
> Tim Fifield

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Re: [PEDA] bug in protel bom generation?

2002-04-12 Thread Brad Velander

Tim,
the first source by which schematic symbols are consolidated is the
PartType field. I couldn't find any Protel documentation which defines the
criteria for consolidation in a BOM but I know it starts with the PartType
field. Don't you think that Protel could give the schematic BOM generation a
bit more then a brief paragraph description in either the online help or the
manual?

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.


> -Original Message-
> From: Tim Fifield [mailto:[EMAIL PROTECTED]]
> Sent: Friday, April 12, 2002 9:34 AM
> To: Protel EDA Form
> Subject: [PEDA] bug in protel bom generation?
> 
> 
> When we generate a BOM in Protel format in P99SE SP6 some parts get
> consolidated even though their libref and several attributes 
> are different.
> Does anybody know why this might be happening?
> 
> Tim Fifield

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[PEDA] bug in protel bom generation?

2002-04-12 Thread Tim Fifield

When we generate a BOM in Protel format in P99SE SP6 some parts get
consolidated even though their libref and several attributes are different.
Does anybody know why this might be happening?

Tim Fifield

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Re: [PEDA] Bug report?

2002-03-01 Thread Dwight

Thomas was referring to Place | Line, not interactive routing, and I can
reproduce the problem.

> -Original Message-
> From: Brad Velander
> Sent: Friday, March 01, 2002 8:37 AM
>
> Andrew or the original poster,
>   yes I get mm as well, as long as I have set metric measures in my
> "O"ptions "B"oard Options window set on P99SE SP6.
>
> Brad Velander.
>
> -Original Message-
> From: Andrew Ircha
> Sent: Friday, March 01, 2002 1:02 AM
>
>
> If I understand you right - that you mean "Interactive routing", I get
> metric units on tab.
>
> -Original Message-
> From: Thomas
> Sent: Thursday, February 28, 2002 7:29 PM

> Summary: 99SESP6 PCB
> While manual routing in 'line' mode, the line constraints dialogue (TAB to
> open), line width field always shows imperial units.
>
> Workaround:
>
> Include metric units string in the field entry box if metric units are
> required, i.e. 0.3mm

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Re: [PEDA] Bug report?

2002-03-01 Thread Brad Velander

Andrew or the original poster,
yes I get mm as well, as long as I have set metric measures in my
"O"ptions "B"oard Options window set on P99SE SP6.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

See us at Booth 323 at Satellite 2002 in Washington, DC March 6-8.



-Original Message-
From: Andrew Ircha [mailto:[EMAIL PROTECTED]]
Sent: Friday, March 01, 2002 1:02 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Bug report?


If I understand you right - that you mean "Interactive routing", I get
metric units on tab.

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[PEDA] Bug report?

2002-02-28 Thread Thomas

Ian, not sure if you have this one (or if you conceder it a bug), as I
haven't had time to look through the database yet.
It's very annoying as I work in metric most of the time.

Summary:

99SESP6 PCB

While manual routing in 'line' mode, the line constraints dialogue (TAB to
open), line width field always shows imperial units.


Workaround:

Include metric units string in the field entry box if metric units are
required, i.e. 0.3mm


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Re: [PEDA] Bug list - maybe - ratsnest

2002-02-28 Thread Abd ul-Rahman Lomax

At 10:37 AM 2/28/2002 -0800, Dennis Saputelli wrote:
>i can't believe i never noticed this or at least that it never bothered
>me before:
>
>the ratsnests disappear in single layer mode (shift S)
>what a shame, it should at least be an option i think to show them

Yes, this is very irritating. One of the main uses for single layer mode is 
judging routability on a single layer, and doing such routing. That the 
connection lines do not display in single layer mode is apparently the 
result of a bad choice on the programmer's part. They knew to allow us to 
include mech layers, but rat's nest lines would be just as important.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Bug list, was Assembly drawing problem

2002-02-28 Thread Mark E Witherite




Re: [PEDA] Bug list - maybe - ratsnest

2002-02-28 Thread Dennis Saputelli

i can't believe i never noticed this or at least that it never bothered
me before:

the ratsnests disappear in single layer mode (shift S)
what a shame, it should at least be an option i think to show them

Dennis Saputelli

-- 
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110

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Re: [PEDA] Bug list, was Assembly drawing problem

2002-02-28 Thread Abd ul-Rahman Lomax

At 09:59 AM 2/28/2002 -0600, Mark E Witherite wrote:
>Also can I get the link to the bug list?

go to http://groups.yahoo.com/group/protel-users/database
and click on Bug List.

You will need to be a member of [EMAIL PROTECTED], and logged in 
to yahoogroups so it can recognize you as such.

(Mr. Witherite is already a member, but yahoogroups periodically insists on 
actual login, even if one has not deleted the cookie)

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA


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Re: [PEDA] BUG REPORT

2002-02-25 Thread Dennis Saputelli

don't know if this has been reported but:

BUG:
Summary: Cannot drag end of unlocked component primitives

Details: Unlocking a component's primitive does not allow dragging of
track ends using the Move Drag End command.
Move Drag doesn't work either. 

Dennis Saputelli

-- 
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110

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Re: [PEDA] BUG??

2002-02-21 Thread Watnoski, Michael




Re: [PEDA] BUG??

2002-02-21 Thread Abd ul-Rahman Lomax

At 01:43 PM 2/21/2002 -0500, Watnoski, Michael wrote:

> I just check and you are correct, except when the display is in
>transparent mode.  In this mode the bottom overlay is always above the
>bottom copper.

In transparent mode, the overlays are transparent. You may not see this if 
you have the overlay set to a bright color or to white, since transparent 
mode adds light, so a white track will display as white no matter what else 
is below or above it.

In other words, the color settings matter. In transparent mode, display 
sequence should be irrelevant.

[EMAIL PROTECTED]
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Easthampton, Massachusetts USA

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Re: [PEDA] BUG??

2002-02-20 Thread Ian Wilson

On 03:52 PM 20/02/2002 -0500, Watnoski, Michael said:
> When the Layout Drawing Order under Tools > Preferences > Display is
>set for Bottom Overlay under Bottom layer, the Bottom overlay is still
>displayed over the Bottom layer.

Michael,

I just checked an I find after I set the Bottom Overlay to lower than 
Bottom Layer in the drawing order, that the overlay is drawn under the 
copper *unless* the overlay is selected as the current layer, in which case 
it is drawn above all the copper layers.

Interestingly, the bottom overlay is drawn *under* the top overlay 
regardless of which layer is active.  The actual draw order is affected by:
1) The Layer Drawing Order set up in Tools-Preferences
2) Which layer is active
3) The layer associations (that is top copper, top overlay, top mask and 
top paste) are all associated.

I suspect that not all the interactions are planned.  This does seem to be 
an area that Protel could do some careful rationalization as the 
relationships are complex enough that the utility of the layer draw order 
dialog is somewhat compromised.

I would like to thrash this around a little more so we can get some sort of 
agreement on what the bug(s) might be.


> Another for the wish list- Final/Draft/Hidden should be set by layer
>- not just by primitive type.

Good idea, I would like that as well.  But I am not maintaining the Wish 
List...

Ian Wilson

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[PEDA] BUG??

2002-02-20 Thread Watnoski, Michael




Re: [PEDA] Bug: display of multilayer primitives

2002-02-19 Thread Ian Wilson

On 03:31 PM 19/02/2002 -0500, Abd ul-Rahman Lomax said:
>As a reminder for Mr. Wilson, preparing a bug list:
>
>The display of "multilayer" objects is seriously flawed. Protel displays 
>"multilayer" objects only if multilayer is enabled. Vias are multilayer 
>objects as currently configured, but vias do not necessarily exist on all 
>layers, they could be blind or buried.

New item added, thanks
Ian Wilson

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[PEDA] Bug: display of multilayer primitives

2002-02-19 Thread Abd ul-Rahman Lomax

As a reminder for Mr. Wilson, preparing a bug list:

The display of "multilayer" objects is seriously flawed. Protel displays 
"multilayer" objects only if multilayer is enabled. Vias are multilayer 
objects as currently configured, but vias do not necessarily exist on all 
layers, they could be blind or buried.

There is presently no way to see only the vias on a single layer or partial 
collection of layers, all vias are either hidden or unconditionally shown 
even if they do not exist on the layers in question.

Single layer mode, I'd suggest, should display multilayer objects unless 
they do not exist on that layer. It is possible that it would be best to 
display the presence of a multilayer object on a layer even if "multilayer" 
is turned off. This is because a multilayer pad *does* live on top and 
bottom and all copper layers, for example. Better development of the 
padstack concept could eliminate the need for "multilayer" entirely, except 
that it is good to be able to quickly distinguish between a single-layer 
pad and one which lives on more than one layer.

The blind/buried via aspect of this is crucial in order to make working 
with blind and buried vias practical.(It is now possible, but one must 
constantly be factoring for the display problem. It is tedious and 
difficult.) The display of other multilayer objects would be an improvement 
and might be accomplished by the same changes that would fix the 
blind/buried via problem.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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[PEDA] Bug (old): Many docs open makes tabs unreliable

2002-02-17 Thread Dwight Harm

Bug (from Feb 2001) for the database?

Summary: Client: If document tabs exceed window width, they become
unreliable.

Details: If enough documents (sch, pcb, text, whatever) are opened so that
the document tabs along the top of the window no longer fit, and scroll
arrows appear, then using the tabs becomes unreliable.  That is, the wrong
document will sometimes be made current.  (Probably at least one tab must be
scrolled completely off the visible area for the problem to occur.)

Submitted by: D. Harm
Confirmed: Gisbert

> -Original Message-
> From: [EMAIL PROTECTED]
> Sent: Friday, February 09, 2001 12:38 AM
> Subject: Re: [PROTEL EDA USERS]: Many docs open makes tabs unreliable. Sp6
bug?
>
> Confirmed. I experienced the same. This is a new bug introduced in SP6.
>
> Gisbert
>
> "Dwight Harm" on 09.02.2001 09:19:00
> Subject:  [PROTEL EDA USERS]:  Many docs open makes tabs unreliable. Sp6
bug?
>
> This problem appears to have just started happening with SP6:  I have a
> single DDB, with its window maximized.  If I open enough
> documents (sch, pcb, text, whatever) so that the document tabs along the
> top of the window no longer fit, and scroll arrows appear,
> then using the tabs becomes unreliable.  That is, the wrong document will
> sometimes be made current.  I think at least one tab must
> be scrolled completely off the visible area for the problem to occur.  It
> happens on 2 different machines, so I don't think it's
> installation or video-card related.  (I first noticed it when
> right-clicking on the tabs, but I think left-clicking fails also.)
> I'm running in 1024x768 mode.

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[PEDA] Bug: unable to change ratsnest lines color

2002-02-16 Thread Dwight Harm

Bug (from last December) for the database?

> -Original Message-
> From: Thomas [mailto:[EMAIL PROTECTED]]
> Sent: Sunday, December 16, 2001 2:47 PM
> Subject: Re: [PEDA] Connection (ratsnest) color (was: How to change
Netlist lines back to solid lines?)
>
> You remember correctly, this does not work for me either (just tried it),
>
> -Original Message-
> From: Dwight Harm [mailto:[EMAIL PROTECTED]]
> Sent: Friday, 14 December 2001 6:23 PM
>
> Setting this color (Options | Colors | Connections) has no effect on my
> system (99SEsp6).  I seem to recall a discussion about this some time ago,
> and no one got it to work.
> So, Tom -- does this actually work for you?

> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, February 13, 2002 11:42 PM
>
> Can I have some assistance pls with people trolling back through the
> archives of this forum looking for things that might be bugs.

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Re: [PEDA] Bug Database - WAS a new bug (or is it?)

2002-02-15 Thread Jason Morgan

We never really got to the bottom of it but we did the following to resolve
it.


Upgrade to W2000 and ban W98 from using protel.
Specify at least 1G RAM
Forbid multiple access of schematics, though we do allow simultanious PCB /
SCH use - reluctantly.
Regularly backup to multiple destinations and keep a 30 deep history of
backups, disk space is plentiful.
Regularly compress the database
If possible store the .DDB on a local machine rather than a server

I think the main cause was W98 and low resources caused by background tasks.
We've not had a corruption in a very long time.

Protels' 'network awairness' is crap, considering its their selling point
its got to be taken with a pinch of
salt.

As I said previously, multiple users of the same .ddb can cause loss of data
as file / record locking is not done
right, its optional and manual.  It should work more like CVS whereby
changes can be merged and controlled.

Also when working on a network copy we get much more frequent 'Protel has
caused a...' messages.

There is somthing really screwy with it.  To give them grace, its probably
not Protel's fault, they are relying
of sombody elses software (JET) to work with multiple users.

J.


-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: 14 February 2002 23:28
To: Protel EDA Forum
Subject: Re: [PEDA] Bug Database - a new bug (or is it?)


On 03:59 PM 14/02/2002 +, Jason Morgan said:
>Here's an interesting 'bug' for the database, or perhaps it will be when
its
>confirmed?
>
>Its not much of one, and I don't want to start a big duscussion on file
>naming.
>
>Try creating a .ddb then save it and exit.
>Rename it to a file with a single quote in it.
>
>e.g.
>MyDatabase.ddb -> Jason's Database.ddb
>
>Then try opening it.
>
>Hmm, where did that database go.

Jason,

There is a Protel KB item on this -  KB Item 1985.

I have been caught by this in the past as well.  But since Protel have the 
KB item I will not add it to the database (unless enough people request 
it).  What I am trying to achieve with the database is some visibility and 
memory of problems that have not made it to the Protel KB or have persisted 
so long that they should have been fixed by now.

Jason - did you get any further in determining why you had a many instances 
of DDB corruption while operating over the network?  This info and any 
warnings you can give would make a good bug database entry( or 
entries).  This is something that Protel KB is not very forthcoming on and 
the marketing bumpf makes claims to network operations.

Ian Wilson

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Re: [PEDA] Bug Database - a new bug (or is it?)

2002-02-14 Thread Ian Wilson

At 05:19 PM 14/02/02 -0800, you wrote:
>The one problem I see is that KB item 1985 indicates it is a user error:
>"Folders cannot contain invalid characters such as apostrophe's."  Since
>Windows allows it as a filename character, it's not invalid; other programs
>handle it ok. Also, equal signs cause a similar problem. (win2000, 99SEsp6)


Yes, I was thinking along similar lines as well since I posted my reply to 
Jason. Your comments crystalise that. Maybe it is worthwhile adding to the 
database as a DDB file name should be able to use *any* valid Windows 
filename.  It is something the Phoenix beta testers should test, so, Yes, I 
will add it to the database.
Ian



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Re: [PEDA] Bug Database - a new bug (or is it?)

2002-02-14 Thread Dwight Harm

The one problem I see is that KB item 1985 indicates it is a user error:
"Folders cannot contain invalid characters such as apostrophe's."  Since
Windows allows it as a filename character, it's not invalid; other programs
handle it ok. Also, equal signs cause a similar problem. (win2000, 99SEsp6)

> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, February 14, 2002 3:28 PM
>
> On 03:59 PM 14/02/2002 +, Jason Morgan said:
> >Try creating a .ddb then save it and exit.
> >Rename it to a file with a single quote in it.
> >e.g.
> >MyDatabase.ddb -> Jason's Database.ddb
> >Then try opening it.
> >
> >Hmm, where did that database go.
>
> Jason,
> There is a Protel KB item on this -  KB Item 1985.
>
> I have been caught by this in the past as well.  But since Protel have the
> KB item I will not add it to the database (unless enough people request
> it).  What I am trying to achieve with the database is some visibility and
> memory of problems that have not made it to the Protel KB or have
persisted
> so long that they should have been fixed by now.

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Re: [PEDA] Bug Database - a new bug (or is it?)

2002-02-14 Thread Ian Wilson

On 03:59 PM 14/02/2002 +, Jason Morgan said:
>Here's an interesting 'bug' for the database, or perhaps it will be when its
>confirmed?
>
>Its not much of one, and I don't want to start a big duscussion on file
>naming.
>
>Try creating a .ddb then save it and exit.
>Rename it to a file with a single quote in it.
>
>e.g.
>MyDatabase.ddb -> Jason's Database.ddb
>
>Then try opening it.
>
>Hmm, where did that database go.

Jason,

There is a Protel KB item on this -  KB Item 1985.

I have been caught by this in the past as well.  But since Protel have the 
KB item I will not add it to the database (unless enough people request 
it).  What I am trying to achieve with the database is some visibility and 
memory of problems that have not made it to the Protel KB or have persisted 
so long that they should have been fixed by now.

Jason - did you get any further in determining why you had a many instances 
of DDB corruption while operating over the network?  This info and any 
warnings you can give would make a good bug database entry( or 
entries).  This is something that Protel KB is not very forthcoming on and 
the marketing bumpf makes claims to network operations.

Ian Wilson

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Re: [PEDA] Bug Database

2002-02-14 Thread Abd ul-Rahman Lomax

At 06:41 PM 2/14/2002 +1100, you wrote:
>I have added a few more entries to the bug database - including a couple 
>of recently discussed bugs.
>
>The general intention of this database is to document bugs that do not 
>seem to make it into the Protel KB, and/or, are persistent bugs that 
>Protel have neglected to fix over a significant period of time.
>
>I am keen to document them so any beta testing of the next version of 
>Protel can include testing of these bugs in the hope that they might get 
>fixed - if enough testers report the bug then maybe it will get fixed.
>
>Can I have some assistance pls with people trolling back through the 
>archives of this forum looking for things that might be bugs.  If you can 
>give me some details (in a form that fits neatly with the database format) 
>that would be great.  Maybe a number of people could organize so that each 
>only had to scan a subsection of the archives.  I s'pose we should try to 
>go back over the last year or so.  We should also remember that not all 
>bug reports have a nice subject line that let us all know that a possible 
>bug is being reported (more's the pity -  a little discipline goes a long 
>way to easing the archivists task).

Yes, but it's not going to happen unless we go to a moderated list, which 
would be counterproductive besides a lot of work. *But* we could set up a 
side-list -- I know you'll love this -- where we, as we go, forward posts 
deemed appropriate for a support database and bug database, and we edit the 
subject lines, using some kind of standard for subject lines -- we need a 
standard because we want to be able to share this duty. A given post might 
in some cases be posted more than once.

As far as sharing the work, I agree that now is the time, actually we 
should have done this sooner at least with the bug aspect. But I'm *really* 
short of time at this point. Nevertheless, I might be able to contribute 
some time. I'd suggest using message numbers on the yahoogroups archive to 
assign chunks. And if one of us takes on a chunk that turns out to be too 
much, it would be easy to then transfer the rest to someone else.

Another idea would be simply to collect message numbers and assign them key 
words. This could easily be made into a set of web pages that would be 
searchable as a single long document without any trouble at all, or perhaps 
as hypertext and I or someone else would have to know how to deal with 
making it easy to search.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Bug Database - a new bug (or is it?)

2002-02-14 Thread Abd ul-Rahman Lomax

At 03:59 PM 2/14/2002 +, Jason Morgan wrote:
>Hry creating a .ddb then save it and exit.
>Rename it to a file with a single quote in it.
>
>e.g.
>MyDatabase.ddb -> Jason's Database.ddb
>
>Then try opening it.
>
>Hmm, where did that database go.

P99SE SP6, W2000, adding the single quote or apostrophe caused Protel not 
to recognise the file, it asks me to add it to a new database. When I 
refused, the file was not overwritten, it was recovered for use by renaming 
it to remove the errant character.

There are certain nonalphanumeric characters that always work in filenames. 
I think that apostrophe is not one of them. I use underscore and hyphen a 
lot, and space now works in Windows, but I like to keep more portability 
and the use of old utilities, etc., so I tend to stick with underscore if a 
space would otherwise be appropriate.

But I no longer try to stay within the 8.3 limits. Good riddance. 
Fortunately DOS -- at least the DOS that comes with Windows with long file 
names allowed -- allows also a method of accessing those long file names 
through an alias.


[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Bug Database - a new bug (or is it?)

2002-02-14 Thread Jason Morgan

Here's an interesting 'bug' for the database, or perhaps it will be when its
confirmed?

Its not much of one, and I don't want to start a big duscussion on file
naming.

Try creating a .ddb then save it and exit.
Rename it to a file with a single quote in it.

e.g.
MyDatabase.ddb -> Jason's Database.ddb

Then try opening it.

Hmm, where did that database go.


J.

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Re: [PEDA] Bug Database (link Included)

2002-02-14 Thread Ian Wilson

On 06:41 PM 14/02/2002 +1100, Ian Wilson said:
>I have added a few more entries to the bug database - including a couple 
>of recently discussed bugs.
>
>The general intention of this database is to document bugs that do not 
>seem to make it into the Protel KB, and/or, are persistent bugs that 
>Protel have neglected to fix over a significant period of time.
>
>I am keen to document them so any beta testing of the next version of 
>Protel can include testing of these bugs in the hope that they might get 
>fixed - if enough testers report the bug then maybe it will get fixed.
>
>Can I have some assistance pls with people trolling back through the 
>archives of this forum looking for things that might be bugs.  If you can 
>give me some details (in a form that fits neatly with the database format) 
>that would be great.  Maybe a number of people could organize so that each 
>only had to scan a subsection of the archives.  I s'pose we should try to 
>go back over the last year or so.  We should also remember that not all 
>bug reports have a nice subject line that let us all know that a possible 
>bug is being reported (more's the pity -  a little discipline goes a long 
>way to easing the archivists task).
>
>Thanks,
>Ian Wilson


Rats!  I meant to put a link to the database in the mail...
http://groups.yahoo.com/group/protel-users/database?method=reportRows&tbl=1&; 
sortBy=1&sortDir=up
will sort in reverse data order

But since long links sometimes get corrupted:
http://groups.yahoo.com/group/protel-users/database?method=reportRows&tbl=1

The Yahoo Groups database layout and searching is crude but works sort 
of.  If anyone has a better web accessible database solution (note the word 
solution) then let me know pls.  I am not interested in being told that I 
*could* go and get all the perl and Java scripts etc that bugzilla have 
released but this assumes I want to spend the time learning how to install 
and make it work on my hosting system ... which at this time I am not.

bye for now,
Ian Wilson

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[PEDA] Bug Database

2002-02-13 Thread Ian Wilson

I have added a few more entries to the bug database - including a couple of 
recently discussed bugs.

The general intention of this database is to document bugs that do not seem 
to make it into the Protel KB, and/or, are persistent bugs that Protel have 
neglected to fix over a significant period of time.

I am keen to document them so any beta testing of the next version of 
Protel can include testing of these bugs in the hope that they might get 
fixed - if enough testers report the bug then maybe it will get fixed.

Can I have some assistance pls with people trolling back through the 
archives of this forum looking for things that might be bugs.  If you can 
give me some details (in a form that fits neatly with the database format) 
that would be great.  Maybe a number of people could organize so that each 
only had to scan a subsection of the archives.  I s'pose we should try to 
go back over the last year or so.  We should also remember that not all bug 
reports have a nice subject line that let us all know that a possible bug 
is being reported (more's the pity -  a little discipline goes a long way 
to easing the archivists task).

Thanks,
Ian Wilson

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Re: [PEDA] bug plotting rotated fill

2001-12-20 Thread Abd ul-Rahman Lomax

At 11:24 AM 12/18/01 -0800, Brad Velander wrote:
>Abd ul-Rahman,
> have you noticed any of the rotated fills where the drawn gerber
>generation leaves gaps in your otherwise solid fill? Like a database that I
>am looking at right now which has approx. 0.5 mil gaps in the gerber draws
>of a Protel fill. Not pretty!

Drawing rotated fills was basically a mistake. Further, it is not easy. 
Protel draws tight fills, i.e., the draws exactly abut their neighbors. 
When you rotate a fill, however, the line endpoints typically become 
irrational numbers, so there is going to be roundoff error, plus there is 
the photoplot rounding. To compensate for this, it would be necessary to 
plot oversize by the appropriate amount, and to correct the fill outline 
accordingly.

*Much* easer to define the macro and specify the rotation, clean and 
simple. At least I think it is, I haven't tried it. I will.



[EMAIL PROTECTED]
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Easthampton, Massachusetts USA

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Re: [PEDA] bug plotting rotated fill

2001-12-18 Thread Brad Velander

Abd ul-Rahman,
have you noticed any of the rotated fills where the drawn gerber
generation leaves gaps in your otherwise solid fill? Like a database that I
am looking at right now which has approx. 0.5 mil gaps in the gerber draws
of a Protel fill. Not pretty!

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, December 18, 2001 10:32 AM
To: Protel EDA Forum
Subject: Re: [PEDA] bug plotting rotated fill




To my mind *any* plot errors are mission-critical. I did receive an 
immediate response from Michelle Covington at Protel US support that she 
verified the problem. I did make it easier for her by providing not only a 
cut-down edition of the problem board file, but also the CAM definitions. 
In any case it was nice to get such a prompt response.



[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] bug plotting rotated fill

2001-12-18 Thread Abd ul-Rahman Lomax

At 03:12 PM 12/17/01 -0800, Leonard Fischer wrote:
>If they don't, or don't quickly enough to do what you need, could you work 
>at some multiplication/magnification of the final scale, say 10x, then 
>just "photographically" reduce the Gerbers?  I'm assuming there is some 
>way to do that (Camtastic?), not that I know how.

The gerbers will be provided to a fabricator who could certainly scale them 
down. It's really only a matter of manipulating an RS-274X parameter.

>This could help with the precision issue in Protel and the magnification 
>in Camtastic.
>
>Just like working with 4x decals and tape!

Yes, though I always worked at 2X. I did do some magnified designs with 
Tango years ago. I wrote a little routine that would magnify a board, it is 
not a difficult problem. It gets a bit more complicated with Protel, what 
with design rules, etc., etc. But still doable. I think it could be done in 
the spreadsheets.

>I'm also assuming that the ceramic module is relatively small compared to 
>a PC Board - I'd be interested in hearing more about the ceramic module, 
>like how big it is and what kind of components you put on it, if that's 
>not proprietary.

Some of it is quite proprietary, NDA and all that. But the process is not 
proprietary. There are a number of fabs, among them National Semiconductor:

http://www.national.com/appinfo/ltcc/0,2583,364,00.html

This particular module has flip-chip ASICs on one side and the other side 
will have micro-machinery added, yes, moving parts The design requires 
using vias at closest spacing, so no tracks between vias in substantial 
areas of the module. Because the module must be designed for more than one 
fab, the design must meet worst-case design rules, which in this case are 2 
mil track and space and 4 mil vias, with 12 mil space between vias (the via 
sizes do not include catchpad, otherwise it would seem that you could put 
track between them. No.) Because the ASICS are basically BGAs at spacings 
inadequate for track between vias, routing is severely constrained and 
reassignment of gates and drivers was necessary to create a routable 
design, even with 21 layers.

The module is 34 mm wide by 127 mm long maximum, i.e., 5 inches. So I could 
work, if necessary, at 10X scale.

There were certain aspects of this job which show the power of the Protel 
spreadsheet for creating complex patterns, I've thought of writing an 
article about it.

However, the design also made very blatant a major bug with blind and 
buried vias, that they display on layers where they do not exist. 
Fortunately, this design turns out to be conceptually easy to understand; 
otherwise it would have been a nightmare and I would have had to move it to 
another CAD system that properly handles blind/buried vias. Right now I 
consider the blind/buried via display problem the worst outstanding issue

A workaround would be to create a pad stack using pads co-incident with the 
via, then suppress the via display. But in this case the database would 
become truly huge, it is already a bit cumbersome to work with, one reason 
I am now assembling a faster computer.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] bug plotting rotated fill

2001-12-18 Thread Abd ul-Rahman Lomax

At 07:52 AM 12/18/01 -0600, Dave Eloranta wrote:
>It would seem that Protel 9SE and Camtastic must
>share some unit conversion code that has a bug.

I doubt that they share code. I'd be interested to look at the actual 
gerber generated with the arc problem that Mr. Eloranta reported.

I looked on the Knowledge Base and was unable to find any articles relating 
to these problems. But it is not necessarily easy to find such

To my mind *any* plot errors are mission-critical. I did receive an 
immediate response from Michelle Covington at Protel US support that she 
verified the problem. I did make it easier for her by providing not only a 
cut-down edition of the problem board file, but also the CAM definitions. 
In any case it was nice to get such a prompt response.

There should be only one round-off in the process: plotting to less than 
full precision or different units (or export to database formats of lower 
precision), and round-off should never be truncation but nearest value, 
even preferred.

Conversion of high-precision units to plot at lower resolution could cause 
various kinds of issues. For example, if a fill draw is rounded down in 
sizeand position, gaps could appear in fills unless the fills were 
overlapped; this should receive special attention.

For some reason, fill routines tend to have had, in my experience, 
problems. Tango never did get it completely right, as I recall. And even 
when the fills were right, they tended to have about twice as many 
primitives as necessary, plus they had problems with intersecting outlines.

Protel does not support, as I noted, true rotation of pads through the plot 
process, they are not flashed, but they are drawn, with an aperture which 
we do not control in RS-274X (we might be able to control it if we use an 
aperture table, which has other problems). So we might think we can make a 
sharp corner with a fill, but it actually turns out rounded if the fill is 
other than orthagonal.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] bug plotting rotated fill

2001-12-18 Thread Dave Eloranta

Leonard
I had a case a few months ago that seems might be related to this unit
conversion problem. I had created a donut shaped fine pitch shield made up
of concentric 4mil arcs, each 8 mil radius larger than the previous arc. The
two sides of the PCB had traces lined up with the spaces on the opposite
side. Each side had about 80 concentric arcs. About 30 arcs into the
structure an error occurred. An arc was skewed. It crossed other arcs. The
matter was not noticed until the board house examined the files with an
independent gerber viewer. Protel 99SE and Camastic both showed this arc in
the proper position while Gcprevue showed it crossing other arcs. To fix it
I drew the arcs in metric units and the arcs appeared properly in both
Camtastic and GCPrevue. It would seem that Protel 9SE and Camtastic must
share some unit conversion code that has a bug.
Dave Eloranta
[EMAIL PROTECTED]

-Original Message-
From:   Leonard Fischer [mailto:[EMAIL PROTECTED]]
Sent:   Monday, December 17, 2001 5:13 PM
To: 'Protel EDA Forum'
Subject:    Re: [PEDA] bug plotting rotated fill

Wow.  That is interesting and kind of amazing that it is workable.  And the
first paragraph where you just said it was a board with submicron precision
really threw me for a loop.

Question/Suggestion/Possibility:

It seems to me that part of the issue here is that Protel and Camtastic are
both designed for larger physical boards.  Ideally of course Altium would
fix the precision issues.  If they don't, or don't quickly enough to do what
you need, could you work at some multiplication/magnification of the final
scale, say 10x, then just "photographically" reduce the Gerbers?  I'm
assuming there is some way to do that (Camtastic?), not that I know how.

This could help with the precision issue in Protel and the magnification in
Camtastic.

Just like working with 4x decals and tape!

I'm also assuming that the ceramic module is relatively small compared to a
PC Board - I'd be interested in hearing more about the ceramic module, like
how big it is and what kind of components you put on it, if that's not
proprietary.

Len Fischer
Trax Softworks

-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Monday, December 17, 2001 11:10 AM
To: Protel EDA Forum
Subject: [PEDA] bug plotting rotated fill


I'm working on a board which requires high precision, in the submicron
range. Theoretically, Protel supports photoplotting with four-place decimal
metric, i.e., one-tenth micron resolution; however, I ran into some
problems with PCB and with CAMtastic.

Rotated fills, which are not flashed but which are drawn, were seen to have
some stray draws. I've sent files to [EMAIL PROTECTED], but for
our bug list, I am also reporting the matter here.

That rotated fills (and pads, I expect) are drawn instead of being flashed
is a bit distressing; this board already generates a lot of data and
drawing those fills will make the gerber files huge. Rectangles (and other
shapes) can be created with RS-274X Aperture Macros, which include a
rotation parameter. They would then also be importable as single primitives
(with appropriately modified gerber import routines.)

Fortunately the fills only occur on one layer which will not be fabricated
with the "PCB" (it is a multilayer co-fired ceramic module) but will be
added later as a separate metalization on the top of the module.

Then, looking at the files in CAMtastic, the aperture tables did not
properly import, there were errors in aperture creation  on the order of
1.5 microns. This is a bit hard to fathom; a metric 150 micron draw
embedded in RS-274X should become, one would think, a 150 micron aperture
in the CAMtastic aperture table, but it doesn't, instead it is 149.9
microns. (Some other apertures had higher deviations.) I'd guess that
metric apertures are being translated to inches on creation, then displayed
back as metric. But the aperture tables were editable to the correct
values, so it is not that the database does not support sufficient
precisions.

However, the maximum zoom level in CAMtastic does not provide as high a
magnification as does PCB, it was barely adequate, if cramped, for working
in the micron range. PCB provides plenty of magnification before it refuses
to zoom in further, it looks to me like roughly 0.1 micron per pixel.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] bug plotting rotated fill

2001-12-17 Thread Leonard Fischer

Wow.  That is interesting and kind of amazing that it is workable.  And the first 
paragraph where you just said it was a board with submicron precision really threw me 
for a loop.

Question/Suggestion/Possibility:

It seems to me that part of the issue here is that Protel and Camtastic are both 
designed for larger physical boards.  Ideally of course Altium would fix the precision 
issues.  If they don't, or don't quickly enough to do what you need, could you work at 
some multiplication/magnification of the final scale, say 10x, then just 
"photographically" reduce the Gerbers?  I'm assuming there is some way to do that 
(Camtastic?), not that I know how.

This could help with the precision issue in Protel and the magnification in Camtastic.

Just like working with 4x decals and tape!

I'm also assuming that the ceramic module is relatively small compared to a PC Board - 
I'd be interested in hearing more about the ceramic module, like how big it is and 
what kind of components you put on it, if that's not proprietary.

Len Fischer
Trax Softworks

-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Monday, December 17, 2001 11:10 AM
To: Protel EDA Forum
Subject: [PEDA] bug plotting rotated fill


I'm working on a board which requires high precision, in the submicron 
range. Theoretically, Protel supports photoplotting with four-place decimal 
metric, i.e., one-tenth micron resolution; however, I ran into some 
problems with PCB and with CAMtastic.

Rotated fills, which are not flashed but which are drawn, were seen to have 
some stray draws. I've sent files to [EMAIL PROTECTED], but for 
our bug list, I am also reporting the matter here.

That rotated fills (and pads, I expect) are drawn instead of being flashed 
is a bit distressing; this board already generates a lot of data and 
drawing those fills will make the gerber files huge. Rectangles (and other 
shapes) can be created with RS-274X Aperture Macros, which include a 
rotation parameter. They would then also be importable as single primitives 
(with appropriately modified gerber import routines.)

Fortunately the fills only occur on one layer which will not be fabricated 
with the "PCB" (it is a multilayer co-fired ceramic module) but will be 
added later as a separate metalization on the top of the module.

Then, looking at the files in CAMtastic, the aperture tables did not 
properly import, there were errors in aperture creation  on the order of 
1.5 microns. This is a bit hard to fathom; a metric 150 micron draw 
embedded in RS-274X should become, one would think, a 150 micron aperture 
in the CAMtastic aperture table, but it doesn't, instead it is 149.9 
microns. (Some other apertures had higher deviations.) I'd guess that 
metric apertures are being translated to inches on creation, then displayed 
back as metric. But the aperture tables were editable to the correct 
values, so it is not that the database does not support sufficient precisions.

However, the maximum zoom level in CAMtastic does not provide as high a 
magnification as does PCB, it was barely adequate, if cramped, for working 
in the micron range. PCB provides plenty of magnification before it refuses 
to zoom in further, it looks to me like roughly 0.1 micron per pixel.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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[PEDA] bug plotting rotated fill

2001-12-17 Thread Abd ul-Rahman Lomax

I'm working on a board which requires high precision, in the submicron 
range. Theoretically, Protel supports photoplotting with four-place decimal 
metric, i.e., one-tenth micron resolution; however, I ran into some 
problems with PCB and with CAMtastic.

Rotated fills, which are not flashed but which are drawn, were seen to have 
some stray draws. I've sent files to [EMAIL PROTECTED], but for 
our bug list, I am also reporting the matter here.

That rotated fills (and pads, I expect) are drawn instead of being flashed 
is a bit distressing; this board already generates a lot of data and 
drawing those fills will make the gerber files huge. Rectangles (and other 
shapes) can be created with RS-274X Aperture Macros, which include a 
rotation parameter. They would then also be importable as single primitives 
(with appropriately modified gerber import routines.)

Fortunately the fills only occur on one layer which will not be fabricated 
with the "PCB" (it is a multilayer co-fired ceramic module) but will be 
added later as a separate metalization on the top of the module.

Then, looking at the files in CAMtastic, the aperture tables did not 
properly import, there were errors in aperture creation  on the order of 
1.5 microns. This is a bit hard to fathom; a metric 150 micron draw 
embedded in RS-274X should become, one would think, a 150 micron aperture 
in the CAMtastic aperture table, but it doesn't, instead it is 149.9 
microns. (Some other apertures had higher deviations.) I'd guess that 
metric apertures are being translated to inches on creation, then displayed 
back as metric. But the aperture tables were editable to the correct 
values, so it is not that the database does not support sufficient precisions.

However, the maximum zoom level in CAMtastic does not provide as high a 
magnification as does PCB, it was barely adequate, if cramped, for working 
in the micron range. PCB provides plenty of magnification before it refuses 
to zoom in further, it looks to me like roughly 0.1 micron per pixel.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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[PEDA] Bug found in placement tools

2001-12-15 Thread Tony Karavidas

I was using the manual interactive placement tool: Align Left.

I had manually aligned a particular jack and then set its properties to
"locked" so it wouldn't move. I then wanted to place another jack in the
same vertical alignment, so I selected both of them and choose "Align Left"
and it MOVED MY LOCKED COMPONENT.

I thought a while back, you could select a group of parts and choose align
whatever, then you could click on the one you want to use for a reference.
When did that disappear?

Ahh. I see what they did. They now choose the "most extreme" location of any
of the selected parts and call that the reference. I was trying to "align
left" and since my locked component was more to the right then the "other"
component, it moved my locked component towards the left. I call this a
minor bug since it moved a locked device without the expected "Selection
contains locked primatives" dialog.

Tony Karavidas
Encore Electronics

http://www.EncoreElectronics.com

Designers of "The best MIDI to CV converter on the planet." -Keyboard Oct.
1997

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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Bagotronix Tech Support

> P.P.S.  I still think it is a bug.

It's not a bug, it's a feature ;-)

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com


- Original Message - 
From: "Jeff Stout" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, December 05, 2001 12:19 PM
Subject: Re: [PEDA] Bug in Interactive Routing


> Yes, I'm following up my own post.
> 
> These should be the rules:
> 
> 1)  If you are on layer 1, and the user tries to
> place a track on a pad on layer 1,  do it.  
> 
> 2)  If you are on layer 1, and the user tries to
> place a track on a pad on layer 2, switch layers
> and start placing tracks on layer 2.
> 
> 3) If you are on layer 1, and there are pads on
> layers 1 and 2.  DO NOT SWITCH LAYERS
> AND START PLACING TRACKS ON LAYER 2!
> 
> Jeff Stout
> 
> P.S.  The layer Protel chooses has something to do with
> which layer you last placed a track on.  If you try to place
> a track on the top pad, it will switch to the bottom pad if
> the last trace you placed was on the bottom layer.  Or something
> like that.
> 
> P.P.S.  I still think it is a bug.


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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Jeff Stout

Yes, I'm following up my own post.

These should be the rules:

1)  If you are on layer 1, and the user tries to
place a track on a pad on layer 1,  do it.  

2)  If you are on layer 1, and the user tries to
place a track on a pad on layer 2, switch layers
and start placing tracks on layer 2.

3) If you are on layer 1, and there are pads on
layers 1 and 2.  DO NOT SWITCH LAYERS
AND START PLACING TRACKS ON LAYER 2!

Jeff Stout

P.S.  The layer Protel chooses has something to do with
which layer you last placed a track on.  If you try to place
a track on the top pad, it will switch to the bottom pad if
the last trace you placed was on the bottom layer.  Or something
like that.

P.P.S.  I still think it is a bug.


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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Jeff Stout

See below:

- Original Message -
From: "Bagotronix Tech Support" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, December 05, 2001 10:10 AM
Subject: Re: [PEDA] Bug in Interactive Routing

[snip]

> connected to the pin of the bottom side chip.  To route to the top chip
> instead, you will need to change the order of the net using the From-To
> editor.  This way you can route to the chip you want to route to first.
>

If I need to edit the From-to list to use the interactive router, this
program
has gone over the edge for ease of use and usefullness.

[snip]

>
> Best regards,
> Ivan Baggett
> Bagotronix Inc.
> website:  www.bagotronix.com
>
>

Jeff Stout


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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Jeff Stout

I pressed the Shift S key and it worked a few times;
but it stopped working.  If I play with it and switch layers
a few times, with a few false starts I can get it to
work again.

I still think it is a bug.

Jeff Stout


- Original Message -
From: "Mike Reagan" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, December 05, 2001 10:18 AM
Subject: Re: [PEDA] Bug in Interactive Routing


>
> Jeff,
> Try pressing Shift S to get you in the Single layer mode, pick up your top
> layer trace off the top pad then continue routing.   It really isnt a bug.
>
>
> Mike Reagan
> EDSI
> Frederick MD USA
>
>
> > I have two memory chips (SSOP56) stacked and aligned
> > on the top layer and bottom layer to take advantage of the
> > space savings.
> >
> > When I go to place a track on a pad on the footprint
> > on the top (red), Protel will switch the track to the bottom
> > layer (blue).  When I mash the TAB keep to fix this problem,
> > Protel wants to insert a via.  I REALLY HATE THIS BUG!
> >
> > You would not believe the contortions I'm going through
> > to place a single track.
> >
> > Jeff Stout
> >
> >
>


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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Bagotronix Tech Support

Jeff:

I don't think this is a bug.  It's a consequence of the way your netlist is
connected.

I think what is happening is that the net you are trying to route is really
connected to the pin of the bottom side chip.  To route to the top chip
instead, you will need to change the order of the net using the From-To
editor.  This way you can route to the chip you want to route to first.

Back in the v2.8 days, this was not a problem because the route would
automagically go to the nearest node (pin) on that net.  But it was a
nuisance if you really wanted to go to a pin beyond that nearest pin first.
So I guess they did away with that feature in later versions.

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com


- Original Message -
From: "Jeff Stout" <[EMAIL PROTECTED]>
To: "Association of Protel EDA Users" <[EMAIL PROTECTED]>
Sent: Wednesday, December 05, 2001 11:04 AM
Subject: [PEDA] Bug in Interactive Routing


> I have two memory chips (SSOP56) stacked and aligned
> on the top layer and bottom layer to take advantage of the
> space savings.
>
> When I go to place a track on a pad on the footprint
> on the top (red), Protel will switch the track to the bottom
> layer (blue).  When I mash the TAB keep to fix this problem,
> Protel wants to insert a via.  I REALLY HATE THIS BUG!
>
> You would not believe the contortions I'm going through
> to place a single track.
>
> Jeff Stout
>
>

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Re: [PEDA] Bug in Interactive Routing

2001-12-05 Thread Mike Reagan


Jeff,
Try pressing Shift S to get you in the Single layer mode, pick up your top
layer trace off the top pad then continue routing.   It really isnt a bug.


Mike Reagan
EDSI
Frederick MD USA


> I have two memory chips (SSOP56) stacked and aligned
> on the top layer and bottom layer to take advantage of the
> space savings.
>
> When I go to place a track on a pad on the footprint
> on the top (red), Protel will switch the track to the bottom
> layer (blue).  When I mash the TAB keep to fix this problem,
> Protel wants to insert a via.  I REALLY HATE THIS BUG!
>
> You would not believe the contortions I'm going through
> to place a single track.
>
> Jeff Stout
>
>

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[PEDA] Bug in Interactive Routing

2001-12-05 Thread Jeff Stout

I have two memory chips (SSOP56) stacked and aligned
on the top layer and bottom layer to take advantage of the
space savings.

When I go to place a track on a pad on the footprint
on the top (red), Protel will switch the track to the bottom
layer (blue).  When I mash the TAB keep to fix this problem,
Protel wants to insert a via.  I REALLY HATE THIS BUG!

You would not believe the contortions I'm going through
to place a single track.

Jeff Stout


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Re: [PEDA] bug report

2001-11-26 Thread Tony Karavidas

I call it a bug. I didn't say it was a big problem, but it's not right. Say
for a moment when Protel was contemplating the feature set of P99SE, they
generated a product requirements document or product specification. Imagine
every parameter and operation were defined properly in this documentation.
Do you think they said:

"Generate XLS file from a PCBlib component. Now if the next operation by the
user is exporting that xls, we write nothing to the disk? I don't think so.
This is a little bug.

My file was actually zero bytes. I'm not sure where you're seeing 4k, but
that's not what I saw.

Tony



> -Original Message-
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: Monday, November 26, 2001 10:39 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] bug report
>
>
> At 09:49 AM 11/26/01 -0800, Tony Karavidas wrote:
> >I just found a little bug.
> >
> >If I export a PCB part to spreadsheet, it works, but if I export THAT
> >outside of the DDB before "saving it" it exports a zero byte
> file. Also, if
> >I look at the .xls file within the DDB, it indicates zero bytes until the
> >ddb is saved. So the internal xls file has data in it, but the project
> >manager claims the file is zero bytes when it isn't.
>
> Bug? Perhaps. Minor quirk might be more like it. The project
> manager claims
> the file is zero bytes because it is empty. Here is how it
> happens, I think:
>
> When a spreadsheet is created by PCB (and I think the same is true for
> Schematic), the file is created but the spreadsheet data is only
> in RAM, it
> is not written to the .ddb. If at this point one closes the .ddb, there
> will be a prompt as to whether or not to save the file. If one saves the
> file, the data is written to the file. If one does *not* save the
> file, an
> empty spreadsheet is maintained in the .ddb.
>
> Yes, it has a size of 4K, I'm not sure why. But it is empty. (perhaps it
> contains formatting defaults or something like that, but it
> definitely does
> not contain the exported data).
>
>
>
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA

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Re: [PEDA] bug report

2001-11-26 Thread Abd ul-Rahman Lomax

At 09:49 AM 11/26/01 -0800, Tony Karavidas wrote:
>I just found a little bug.
>
>If I export a PCB part to spreadsheet, it works, but if I export THAT
>outside of the DDB before "saving it" it exports a zero byte file. Also, if
>I look at the .xls file within the DDB, it indicates zero bytes until the
>ddb is saved. So the internal xls file has data in it, but the project
>manager claims the file is zero bytes when it isn't.

Bug? Perhaps. Minor quirk might be more like it. The project manager claims 
the file is zero bytes because it is empty. Here is how it happens, I think:

When a spreadsheet is created by PCB (and I think the same is true for 
Schematic), the file is created but the spreadsheet data is only in RAM, it 
is not written to the .ddb. If at this point one closes the .ddb, there 
will be a prompt as to whether or not to save the file. If one saves the 
file, the data is written to the file. If one does *not* save the file, an 
empty spreadsheet is maintained in the .ddb.

Yes, it has a size of 4K, I'm not sure why. But it is empty. (perhaps it 
contains formatting defaults or something like that, but it definitely does 
not contain the exported data).



[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] bug report

2001-11-26 Thread Brad Velander

Tony,
I ran into that little bug while taking the Protel training in Sept
2000. It drove me and the instructor, who also couldn't figure out the
problem, nuts for about 15 minutes. I couldn't export the file that the
instructor was trying to have us export. Someone might think that they would
fix little issues like that, especially when their instructors or other
Protel staffers find them or experience them.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent: Monday, November 26, 2001 9:50 AM
To: Protel EDA Forum
Subject: Re: [PEDA] bug report


I just found a little bug.

If I export a PCB part to spreadsheet, it works, but if I export THAT
outside of the DDB before "saving it" it exports a zero byte file. Also, if
I look at the .xls file within the DDB, it indicates zero bytes until the
ddb is saved. So the internal xls file has data in it, but the project
manager claims the file is zero bytes when it isn't.

Tony

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Re: [PEDA] bug report

2001-11-26 Thread Tony Karavidas

I just found a little bug.

If I export a PCB part to spreadsheet, it works, but if I export THAT
outside of the DDB before "saving it" it exports a zero byte file. Also, if
I look at the .xls file within the DDB, it indicates zero bytes until the
ddb is saved. So the internal xls file has data in it, but the project
manager claims the file is zero bytes when it isn't.

Tony

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Re: [PEDA] BUG.... Error handling BOM generation

2001-10-02 Thread Abd ul-Rahman Lomax

***
Todays forums are sponsored by Ian Martin Limited
Engineering/Technical Placement Specialists
www.ianmartin.com
***

At 02:50 PM 10/1/01 -0700, Brooks,Bill wrote:
>the BOM utility doesn't know how to deal with a
>board with zero parts on it.  So it hangs...

Ian has verified this, but it is not surprising. Yes, it's a bug; but who 
would have thought that you might want to generate a BOM for a board with 
no parts on it? In other words, the bug exists because no one ever tried 
this before.

It should be mentioned that the immediate solution is to delete the BOM 
from the CAM setups for that board, just in case someone does not realize that.



[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] BUG.... Error handling BOM generation

2001-10-01 Thread Ian Wilson

***
Todays forums are sponsored by Ian Martin Limited
Engineering/Technical Placement Specialists
www.ianmartin.com
***

On 02:50 PM 1/10/2001 -0700, Brooks,Bill said:
>Found an unusual bug When generating the CAM files, I usually include
>the BOM generation. I have a PCB without parts on it... it's a printed
>spiral inductor. I ran the CAM files like usual, and the BOM utility would
>not finish ran and ran and ran... Had to terminate Protel 99SE from the
>Task Manager. My guess is, the BOM utility doesn't know how to deal with a
>board with zero parts on it.  So it hangs... anyone else seen this?
>
>Bill Brooks

Yep, I agree.  It is a bug of sorts.

If you run the PCB BOM Wizard on a component-less PCB it gives a warning 
dialog saying "no components found" or words to that effect.

But when run through the CAM Manager it crashes - I also got an access 
violation but maybe that is due to another bug. I asked for an NC-Drill 
report on a board with no holes.  So maybe there is a problem with NC-Drill 
on a hole-less PCB as well.  more investogation warranted if someone has 
the time...

I ignored the AV and then saw what Bill saw - the BOM report generation 
hanging.  Task Man required to kill P99SE.

Bug.  I will try to get on and update the last 10 bugs into the bug 
database.  I would like some scripting capability in CAM Manager then we 
could work around such problems as this by adding conditionals such as (in 
pseudo-psuedocode):
  if NumComponents > 0 then
  GeneratePCBBOM

Such scripting would also allow (hopefully) access to the PCB design rules 
so that, for instance, one could adjust clearances or mask expansions etc 
between layers.

Ian

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[PEDA] BUG.... Error handling BOM generation

2001-10-01 Thread Brooks,Bill

***
Todays forums are sponsored by Ian Martin Limited
Engineering/Technical Placement Specialists
www.ianmartin.com
***

Found an unusual bug When generating the CAM files, I usually include
the BOM generation. I have a PCB without parts on it... it's a printed
spiral inductor. I ran the CAM files like usual, and the BOM utility would
not finish ran and ran and ran... Had to terminate Protel 99SE from the
Task Manager. My guess is, the BOM utility doesn't know how to deal with a
board with zero parts on it.  So it hangs... anyone else seen this?

Bill Brooks 
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court 
Vista, CA 92083 
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 
mailto:[EMAIL PROTECTED] 
IPC Designers Council, San Diego Chapter 
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm

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Re: [PEDA] Bug query?

2001-09-21 Thread Jim Parr

Hi Folks,

And not only that --

When top Cu. layer is OFF - invisible, you cannot select components from the
top overlay or bottom Cu for many of the select menus.  This is only an
issue if you have (needlessly for the most part) switched off top layer
because you are working on a simple single-side, leaded board.

I also find I have lots of conceptual problems when selectively moving
primitives between layers.  I end up having to do this quite often (move or
copy) between mechanical layers.  There is always a way to get it done but I
wish I could figure out how to set up a "select on current layer" mode and
race around selecting only those bits & bobs I want on current layer only.
If there is a standard option to accomplish this I haven't found it yet.

While in moan mode - does anyone know how to set up 'dimension' display for
printing/viewing with values truncated to 'n' significant digits or decimal
places?

Any ideas out there?

Regards all,
Jim Parr




- Original Message -
From: Frank Gilley <[EMAIL PROTECTED]>
To: Protel EDA Forum <[EMAIL PROTECTED]>
Sent: Tuesday, 18 September 2001 10:14
Subject: Re: [PEDA] Bug query?


> I have tried this... and he's right, it won't select through-hole
> components if they are designated as being on the TOP layer.
Through-holes
> mounted from the BOTTOM layer will select.  Exception:  Free pads will
> select no matter what.
> Protel definitely doesn't like its top-layer being turned off.  If you do
> single-siders, leave the top layer on and just don't put any tracks on
> it/don't generate any gerbers for that layer.
>
> As to whether or not this is a bug...hmmm we'd have to take a vote.
>
> Frank
>
>
> At 05:01 PM 9/17/2001 -0500, Jon wrote:
>
>
> >Richard Thompson wrote:
> >
> > > Hi group
> > >
> > > Can anyone confirm if this is a bug or not please?
> > >
> > > in protel 99se pcb editor.  if i click left mouse and drag over
components
> > > to select them it only selects the surface mount components and not
> > > conventional through hole.  This is on a simple single sided board
with
> > > mixed SMD and through hole comps. (multi layer is on, as is bottom
artwork
> > > etc but not top artwork)
> >
> >Wierd!  I can assure you it doesn't behave like that for me, on typical
> >2 or 4 layer boards.
> >
> > > If i turn the top layer on (which i'm not using) the click drag works
fine
> > > and selects all components properly. The top layer does not have to be
> > > selected as current, it mearly has to be active in design/options.
> > > SMD parts are on bottom artwork layer only, through hole pads are
> > multilayer
> > > (using pad stack for different sizes.  Obviously the multilayer pads
> > are the
> > > problem but why?
> >
> >Well, designing a board with no top copper is kind of strange.  If there
> >is only one copper layer, maybe you should call that top copper, and
> >not design the board from the opposite side.
> >
> > >
> > > Its not a problem as such but surely it shouldn't behave like this?
> >
> >It is quite conceivable that noone ever tried this!
> >
> >Jon
>
> Frank Gilley
> Dell-Star Technologies
> (918) 838-1973 Phone
> (918) 838-8814 Fax
> [EMAIL PROTECTED]
> http://www.dellstar.com

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Re: [PEDA] Bug query?

2001-09-17 Thread Dennis Saputelli

acad has a neat way of dealing with the selection window i think protel should
steal

if you draw the window from upper left to lower right it only selects objects
which are completely enclosed (aka "window")
if you draw the window from lower right to upper left it selects anything within
or touching the window bounding box (aka "crossing")

that wouldn't make life too much harder and would be very useful i think

we hosed a bd once which we probably wouldn't have if that "crossing" feature
was there

Dennis Saputelli


Bruce Walter wrote:

> Sure, I can see the usefulness of this.
>
> However, since free pads and vias are not ON any 'layer', having a mechanism
> to distinguish between when you do, and when you don't want to include these
> items.
>
> Also, I would imagine that you might want to include SOME items, but not
> others.
>
> When I want to make selections that are exacting - especially when in the
> midst of other items, I take advantage of the fact that Protel only selects
> items that are COMPLETELY surrounded by the drag box.  It may take several
> box drags, but since they are additive, it isn't too bad.  Then I
> shift-click the remaining details.
>
> I don't see a much easier way to get EXACTLY what you want.  We need to be
> careful that adding too much functionality, flexibility and options doesn't
> make a product unusable, too expensive, and too difficult to learn.
>
> -Original Message-
> From: Frank Gilley [mailto:[EMAIL PROTECTED]]
> Sent: Monday, September 17, 2001 3:57 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Bug query?
>
> Ok, I'm willing to go along with that thinking, however it would be more
> useful to me if it were possible to exclude free pads & especially vias
> from selection when using this method.
>
> Frank
>
> At 03:35 PM 9/17/2001 -0700, Bruce wrote:
> >This is no bug.  This is Protel operating as it is designed.
> >
> >If you turn off a layer, it is assumed that you do not want to manipulate
> >items on that layer!
> >
> >So, by placing components on (in this case) the top layer, then turning off
> >the top layer, I would EXPECT it to not be selectable, in spite of the fact
> >that it might have some multi-layer primitives that show even when that
> >layer it turned off.
> >
> >Seems to be behaving as expected to me...

--
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street
  fax: 415-647-3003San Francisco, CA 94110


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Re: [PEDA] Bug query?

2001-09-17 Thread Bruce Walter

Sure, I can see the usefulness of this.

However, since free pads and vias are not ON any 'layer', having a mechanism
to distinguish between when you do, and when you don't want to include these
items.

Also, I would imagine that you might want to include SOME items, but not
others.

When I want to make selections that are exacting - especially when in the
midst of other items, I take advantage of the fact that Protel only selects
items that are COMPLETELY surrounded by the drag box.  It may take several
box drags, but since they are additive, it isn't too bad.  Then I
shift-click the remaining details.

I don't see a much easier way to get EXACTLY what you want.  We need to be
careful that adding too much functionality, flexibility and options doesn't
make a product unusable, too expensive, and too difficult to learn.



-Original Message-
From: Frank Gilley [mailto:[EMAIL PROTECTED]]
Sent: Monday, September 17, 2001 3:57 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Bug query?


Ok, I'm willing to go along with that thinking, however it would be more 
useful to me if it were possible to exclude free pads & especially vias 
from selection when using this method.

Frank

At 03:35 PM 9/17/2001 -0700, Bruce wrote:
>This is no bug.  This is Protel operating as it is designed.
>
>If you turn off a layer, it is assumed that you do not want to manipulate
>items on that layer!
>
>So, by placing components on (in this case) the top layer, then turning off
>the top layer, I would EXPECT it to not be selectable, in spite of the fact
>that it might have some multi-layer primitives that show even when that
>layer it turned off.
>
>Seems to be behaving as expected to me...

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Re: [PEDA] Bug query?

2001-09-17 Thread Frank Gilley

Ok, I'm willing to go along with that thinking, however it would be more 
useful to me if it were possible to exclude free pads & especially vias 
from selection when using this method.

Frank

At 03:35 PM 9/17/2001 -0700, Bruce wrote:
>This is no bug.  This is Protel operating as it is designed.
>
>If you turn off a layer, it is assumed that you do not want to manipulate
>items on that layer!
>
>So, by placing components on (in this case) the top layer, then turning off
>the top layer, I would EXPECT it to not be selectable, in spite of the fact
>that it might have some multi-layer primitives that show even when that
>layer it turned off.
>
>Seems to be behaving as expected to me...

Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Bug query?

2001-09-17 Thread Bruce Walter

This is no bug.  This is Protel operating as it is designed.

If you turn off a layer, it is assumed that you do not want to manipulate
items on that layer!

So, by placing components on (in this case) the top layer, then turning off
the top layer, I would EXPECT it to not be selectable, in spite of the fact
that it might have some multi-layer primitives that show even when that
layer it turned off.

Seems to be behaving as expected to me...

-Original Message-
From: Frank Gilley [mailto:[EMAIL PROTECTED]]
Sent: Monday, September 17, 2001 3:15 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Bug query?


I have tried this... and he's right, it won't select through-hole 
components if they are designated as being on the TOP layer.  Through-holes 
mounted from the BOTTOM layer will select.  Exception:  Free pads will 
select no matter what.
Protel definitely doesn't like its top-layer being turned off.  If you do 
single-siders, leave the top layer on and just don't put any tracks on 
it/don't generate any gerbers for that layer.

As to whether or not this is a bug...hmmm we'd have to take a vote.

Frank

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Re: [PEDA] Bug query?

2001-09-17 Thread Frank Gilley

I have tried this... and he's right, it won't select through-hole 
components if they are designated as being on the TOP layer.  Through-holes 
mounted from the BOTTOM layer will select.  Exception:  Free pads will 
select no matter what.
Protel definitely doesn't like its top-layer being turned off.  If you do 
single-siders, leave the top layer on and just don't put any tracks on 
it/don't generate any gerbers for that layer.

As to whether or not this is a bug...hmmm we'd have to take a vote.

Frank


At 05:01 PM 9/17/2001 -0500, Jon wrote:


>Richard Thompson wrote:
>
> > Hi group
> >
> > Can anyone confirm if this is a bug or not please?
> >
> > in protel 99se pcb editor.  if i click left mouse and drag over components
> > to select them it only selects the surface mount components and not
> > conventional through hole.  This is on a simple single sided board with
> > mixed SMD and through hole comps. (multi layer is on, as is bottom artwork
> > etc but not top artwork)
>
>Wierd!  I can assure you it doesn't behave like that for me, on typical
>2 or 4 layer boards.
>
> > If i turn the top layer on (which i'm not using) the click drag works fine
> > and selects all components properly. The top layer does not have to be
> > selected as current, it mearly has to be active in design/options.
> > SMD parts are on bottom artwork layer only, through hole pads are 
> multilayer
> > (using pad stack for different sizes.  Obviously the multilayer pads 
> are the
> > problem but why?
>
>Well, designing a board with no top copper is kind of strange.  If there
>is only one copper layer, maybe you should call that top copper, and
>not design the board from the opposite side.
>
> >
> > Its not a problem as such but surely it shouldn't behave like this?
>
>It is quite conceivable that noone ever tried this!
>
>Jon

Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Bug query?

2001-09-17 Thread Jon Elson



Richard Thompson wrote:

> Hi group
>
> Can anyone confirm if this is a bug or not please?
>
> in protel 99se pcb editor.  if i click left mouse and drag over components
> to select them it only selects the surface mount components and not
> conventional through hole.  This is on a simple single sided board with
> mixed SMD and through hole comps. (multi layer is on, as is bottom artwork
> etc but not top artwork)

Wierd!  I can assure you it doesn't behave like that for me, on typical
2 or 4 layer boards.

> If i turn the top layer on (which i'm not using) the click drag works fine
> and selects all components properly. The top layer does not have to be
> selected as current, it mearly has to be active in design/options.
> SMD parts are on bottom artwork layer only, through hole pads are multilayer
> (using pad stack for different sizes.  Obviously the multilayer pads are the
> problem but why?

Well, designing a board with no top copper is kind of strange.  If there
is only one copper layer, maybe you should call that top copper, and
not design the board from the opposite side.

>
> Its not a problem as such but surely it shouldn't behave like this?

It is quite conceivable that noone ever tried this!

Jon

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[PEDA] Bug: UPDATE to Problem Found (Ex: Mechanikal Layers are disappearing)

2001-09-17 Thread Ian Wilson

On 09:35 PM 17/09/2001 +1000, Ian Wilson said:

>To fix it I replaced the LayerDrawingOrder0 to LayerDrawingOrder82 entries 
>in the ADVPCB99se.ini with those copied from my backed-up 
>version.  Pressing the Default button on the Layer Drawing Order dialog 
>did not fix it.


I wrote that pressing the Default button in the Layer Drawing Order dialog 
does not fix the problem - worse than that it *causes* it.  If you click 
the Default button you loose quite a few layers from the layer order list - 
looks like the default button function was not updated for the additional 
layers in P99SE - a bit careless.

So - do *not* press the Default button in the Layer Drawing Order dialog.

Protel CSC, could you pls add the relevant KB item and ensure this gets fixed.

Ian





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Re: [PEDA] Bug query?

2001-09-17 Thread HxEngr
 


Re: [PEDA] Bug query?

2001-09-17 Thread Aalt Lokhorst

> If i turn the top layer on (which i'm not using) 

I think your through hole components are placed on the toplayer.

Aalt Lokhorst (e-mail [EMAIL PROTECTED])

address:
  Schut Geometrische Meettechniek bv
  Duinkerkenstraat 21
  9723 BN  Groningen, The Netherlands
  tel. +31 50-5877877
  fax. +31 50-5877899

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[PEDA] Bug query?

2001-09-17 Thread Richard Thompson

Hi group

Can anyone confirm if this is a bug or not please?

in protel 99se pcb editor.  if i click left mouse and drag over components
to select them it only selects the surface mount components and not
conventional through hole.  This is on a simple single sided board with
mixed SMD and through hole comps. (multi layer is on, as is bottom artwork
etc but not top artwork) 
If i turn the top layer on (which i'm not using) the click drag works fine
and selects all components properly. The top layer does not have to be
selected as current, it mearly has to be active in design/options.
SMD parts are on bottom artwork layer only, through hole pads are multilayer
(using pad stack for different sizes.  Obviously the multilayer pads are the
problem but why?

Its not a problem as such but surely it shouldn't behave like this?  

Rich

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Re: [PEDA] Bug List - better implementation desired

2001-09-06 Thread Ian Wilson

On 02:17 PM 6/09/2001 -0700, Abd ul-Rahman Lomax said:
>At 09:10 AM 9/6/01 +1000, Ian Wilson wrote:
>>I am searching (part time) for a better method of maintaining the bug 
>>list.  I am thinking something along the lines of the Bugzilla project as 
>>used by the Mozilla people (http://www.mozilla.org/bugs/).  Or something 
>>similar.
>>
>>What I would like is:
>>1) easy entry and editing (by one or more admin people)
>>2) able to act as store for more than just bugs, also suggestions
>>3) ability to maintain a status on each bug/suggestion - such as fixed 
>>and in what version it was fixed
>>4) more powerful search
>>5) Maybe the ability to accept ongoing comments from users (possibly 
>>moderated) and maintain the thread to allow issues to be 
>>discussed.  (This should not be confused as another mailing list, that is 
>>not the function.)
>>6) ability to include graphics in posts maybe to allow screen shots to be 
>>included - although these could be links to external pages.
>>
>>My problem is I do not know much about Perl/CGI/webby stuff.  So I am not 
>>sure how one would go about installing this, getting the source etc.
>>
>>I am enlisting a couple of people who think they can offer some time and 
>>expertise to help set up a better bug/suggestion tracking system. Frankly 
>>I do not want to get too involved in the nitty gritty apart from 
>>commenting on the solutions that others dig up.  Anyon got the skills 
>>required?  I am not too interested in "I would like to help but have not 
>>got the time".  None of us have.  If you were going to write along those 
>>lines just don't write, thanks.


>Hmmm... Most of the desired qualities are already in place, using the 
>associated list [EMAIL PROTECTED]

Not really - mailing lists do not search well, and there is much clicking 
to follow threads.  Editing data and appending new info is messy.   I am 
looking for an independent (of Protel) KB sort of things that allows 
tracking of bugs and suggestions.  This function is not served well by a 
mailing list - moderated or not.  The combination of the Yahoo database and 
the supporting mailing list is workable but not ideal.

The yahoo database function is too limited for what I want.  Grafting on 
additional functionality by linking to mailing lists is a work-around.  As 
we move to a more professional footing I see value in getting the PrU-KB 
into one location (that can be backed up).  with easy edits.  The display 
formatting of the yahoo database is not ideal and has lots of clutter.

Thanks for the comments,
Ian

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Re: [PEDA] Bug List - better implementation desired

2001-09-06 Thread Abd ul-Rahman Lomax

At 09:10 AM 9/6/01 +1000, Ian Wilson wrote:
>I am searching (part time) for a better method of maintaining the bug 
>list.  I am thinking something along the lines of the Bugzilla project as 
>used by the Mozilla people (http://www.mozilla.org/bugs/).  Or something 
>similar.
>
>What I would like is:
>1) easy entry and editing (by one or more admin people)
>2) able to act as store for more than just bugs, also suggestions
>3) ability to maintain a status on each bug/suggestion - such as fixed and 
>in what version it was fixed
>4) more powerful search
>5) Maybe the ability to accept ongoing comments from users (possibly 
>moderated) and maintain the thread to allow issues to be discussed.  (This 
>should not be confused as another mailing list, that is not the function.)
>6) ability to include graphics in posts maybe to allow screen shots to be 
>included - although these could be links to external pages.
>
>My problem is I do not know much about Perl/CGI/webby stuff.  So I am not 
>sure how one would go about installing this, getting the source etc.
>
>I am enlisting a couple of people who think they can offer some time and 
>expertise to help set up a better bug/suggestion tracking system. Frankly 
>I do not want to get too involved in the nitty gritty apart from 
>commenting on the solutions that others dig up.  Anyon got the skills 
>required?  I am not too interested in "I would like to help but have not 
>got the time".  None of us have.  If you were going to write along those 
>lines just don't write, thanks.

Hmmm... Most of the desired qualities are already in place, using the 
associated list [EMAIL PROTECTED] As it was started, the 
list was open to posting by any member and any editing (i.e., removal of 
posts not relevant to the purpose of the list) was to be post-facto. This 
was because it was considered to be much less work than having a moderator 
approve all the post. But Mr. Wilson proposed to the association that the 
list be a priori moderated and his proposal prevailed, over my objection, 
by vote of the association.

As it was conceived, reports in the bug database (which should be renamed 
the "issues" database to reflect Protel usage which includes suggestions) 
would contain a URL to a thread in the issues mailing list. That satisfies 
number 5 above. At least one bug report has such a link.

Making it unmoderated could be done at any time: moderation mostly adds 
work, in my opinion, given that the list rules allow the moderators to 
delete posts and threads. But if Mr. Wilson wishes to continue moderating 
the list, I'm certainly not going to go back to the association to request 
a reconsideration (but any member who voted for moderating the list could 
make such a request).

Mr. Wilson has frequently expressed his aversion to creating more mailing 
lists. It's beyond me why. The list was conceived as a convenient *storage* 
place for user comments, not as a discussion list, per se. But because it 
*is* a yahoogroups list, anyone can choose to be notified when something is 
added to it by joining and setting one's options to receive list mail.

Anyway, that anyone can post (or submit a post) to the list satisfies item 
(1) above. Number (2) is already there, really, the only barrier would be a 
refusal by a moderator to accept a post to the list that was a suggestion 
rather than a bug report.

Number 3, status information, would simply be a field in the existing 
database. Isn't it already there? Further, any thread on the commentary 
list could contain status updates. That, again, was how the list was conceived.

As to a more powerful search, number 4, the list is already indexed by the 
major search engines (or could be), but anyone could host an index to the 
list, or it could be placed in the filespace for protel-users-issues. 
Graphics could likewise be in that filespace or externally hosted. The 
central issues database, or its index, should not contain graphics, which 
are likely to increase load times. It's enough that links be present where 
graphics are appropriate. If these links are set to open a new browser 
window, it would be even better.

In other words, we already have what Mr. Wilson wants; what is missing is 
additional work to flesh it out or improve it.

>Where it gets hosted is another discussion that will no doubt get a lively 
>discussion going (my thought www.protelusers.net - but that doesn't 
>exist...yet.  protelusers.net should no be tied too closely to any company.

protelusers.net exists already, together with the .com and .org variations. 
It apparently is not hosted. Care to guess who owns the names? One hint: it 
isn't me.

I just registered protel-users.org on behalf of the association, as I have 
reported on the association list ([EMAIL PROTECTED] 
That includes free web address forwarding, so the actual web page -- or, 
really, an index to the web *pages*, could be hosted anywhere. I've got 
lots of filespace available (on lomaxdesign.com)

[PEDA] Bug List - better implementation desired

2001-09-05 Thread Ian Wilson

Hello all,

I am searching (part time) for a better method of maintaining the bug 
list.  I am thinking something along the lines of the Bugzilla project as 
used by the Mozilla people (http://www.mozilla.org/bugs/).  Or something 
similar.

What I would like is:
1) easy entry and editing (by one or more admin people)
2) able to act as store for more than just bugs, also suggestions
3) ability to maintain a status on each bug/suggestion - such as fixed and 
in what version it was fixed
4) more powerful search
5) Maybe the ability to accept ongoing comments from users (possibly 
moderated) and maintain the thread to allow issues to be discussed.  (This 
should not be confused as another mailing list, that is not the function.)
6) ability to include graphics in posts maybe to allow screen shots to be 
included - although these could be links to external pages.

My problem is I do not know much about Perl/CGI/webby stuff.  So I am not 
sure how one would go about installing this, getting the source etc.

I am enlisting a couple of people who think they can offer some time and 
expertise to help set up a better bug/suggestion tracking system. Frankly I 
do not want to get too involved in the nitty gritty apart from commenting 
on the solutions that others dig up.  Anyon got the skills required?  I am 
not too interested in "I would like to help but have not got the 
time".  None of us have.  If you were going to write along those lines just 
don't write, thanks.

Where it gets hosted is another discussion that will no doubt get a lively 
discussion going (my thought www.protelusers.net - but that doesn't 
exist...yet.  protelusers.net should no be tied too closely to any company.

Ian Wilson

Considered Solutions Pty Ltd mailto:[EMAIL PROTECTED]
ABN: 96 088 410 002
5 The Crescent
CHATSWOOD   2067
Ph: +61 2 9411 4248   Fax: +61 2 9411 4249

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Re: [PEDA] Bug when opening Protel

2001-07-18 Thread ga

Thank you, Konrad, that's a nice work-around.

Gisbert Auge



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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Konrad Iten

Gruezi Edi

It's under "System Preferences" and it's the last line.
Don't why you don't have it. I'm running WinME.


Konrad

- Original Message -
From: "Edi Im Hof" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, 17 July, 2001 2:04 PM
Subject: Re: [PEDA] Bug when opening Protel


> Hmm, it seems everybody has such an entry in the ini file. I haven't.
> But I have the splash screen, so the default setting seems to be "true".
> In with section of the ini file has this line to be?
>
> Edi
>
> PS: I've looked in the client99se.ini in the winnt directory.
>
> At 12:41 17.07.01 -0700, you wrote:
> >This is great!
> >
> >This problem has been around since Protel 98.  I always was careful to
wait
> >until the splash goes away before minimizing - but this is better!
> >
> >-Original Message-
> >From: Konrad Iten [mailto:[EMAIL PROTECTED]]
> >Sent: Tuesday, July 17, 2001 11:37 AM
> >To: Protel EDA Forum
> >Subject: Re: [PEDA] Bug when opening Protel
> >
> >
> >Hi
> >
> >In the Client99SE.ini under system preferences is a line called
> >"DisplaySplashScreen=True".
> >Just change true to false and there will be no splash screen anymore.
> >
> >Enjoy
> >  Konrad
> >

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Edi Im Hof

Hmm, it seems everybody has such an entry in the ini file. I haven't.
But I have the splash screen, so the default setting seems to be "true".
In with section of the ini file has this line to be?

Edi

PS: I've looked in the client99se.ini in the winnt directory.

At 12:41 17.07.01 -0700, you wrote:
>This is great!
>
>This problem has been around since Protel 98.  I always was careful to wait
>until the splash goes away before minimizing - but this is better!
>
>-Original Message-
>From: Konrad Iten [mailto:[EMAIL PROTECTED]]
>Sent: Tuesday, July 17, 2001 11:37 AM
>To: Protel EDA Forum
>Subject: Re: [PEDA] Bug when opening Protel
>
>
>Hi
>
>In the Client99SE.ini under system preferences is a line called
>"DisplaySplashScreen=True".
>Just change true to false and there will be no splash screen anymore.
>
>Enjoy
>  Konrad
>

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread HxEngr
 


Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Bruce Walter

This is great!

This problem has been around since Protel 98.  I always was careful to wait
until the splash goes away before minimizing - but this is better!

-Original Message-
From: Konrad Iten [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 17, 2001 11:37 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Bug when opening Protel


Hi

In the Client99SE.ini under system preferences is a line called
"DisplaySplashScreen=True".
Just change true to false and there will be no splash screen anymore.

Enjoy
 Konrad


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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Tony Karavidas

Well that's cool. But it's no excuse for the problem. It is a handy
"temporary" fix however! :)

Thanks!!

Tony


> -Original Message-
> From: Konrad Iten [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, July 17, 2001 11:37 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Bug when opening Protel
>
>
> Hi
>
> In the Client99SE.ini under system preferences is a line called
> "DisplaySplashScreen=True".
> Just change true to false and there will be no splash screen anymore.
>
> Enjoy
>  Konrad
>
>
> - Original Message -
> From: "Tony Karavidas" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Tuesday, 17 July, 2001 11:30 AM
> Subject: Re: [PEDA] Bug when opening Protel
>
>
> > I see it too:
> >
> > Windows 2000, SP2 on an AMD 900MHz system with a Geforce2MX card.
> >
> > Tony
> >
> >
> > > Hi,
> > >
> > > I just noticed a bug which was new to me so far.
> > >
> > > If you open Protel and click on the little "minimize window" button in
> the
> > > upper right window corner while the files are loading, and then renew
> the
> > > normal window size some time later, the entrance picture "Design
> Explorer
> > > 99 SE" does not close, although the database has been opened in the
> > > background. No way to make it disappear. You have to close the
> application
> > > completely and start it anew (and keep the window open during file
> loading
> > > time).
> > >
> > > Not really serious, but a bug.
> > >
> > > Regards,
> > >
> > > Gisbert Auge
> > >
>
>

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Abd ul-Rahman Lomax

At 11:36 AM 7/17/01 -0700, Konrad Iten wrote:
>In the Client99SE.ini under system preferences is a line called
>"DisplaySplashScreen=True".
>Just change true to false and there will be no splash screen anymore.

I too had been afflicted by this annoying little bug and had not noticed 
the conditions under which it bites; it was easy enough, if irritating, to 
close down Protel and restart it. Mr Iten's fix is much appreciated.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Konrad Iten

Hi

In the Client99SE.ini under system preferences is a line called
"DisplaySplashScreen=True".
Just change true to false and there will be no splash screen anymore.

Enjoy
 Konrad


- Original Message -
From: "Tony Karavidas" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, 17 July, 2001 11:30 AM
Subject: Re: [PEDA] Bug when opening Protel


> I see it too:
>
> Windows 2000, SP2 on an AMD 900MHz system with a Geforce2MX card.
>
> Tony
>
>
> > Hi,
> >
> > I just noticed a bug which was new to me so far.
> >
> > If you open Protel and click on the little "minimize window" button in
the
> > upper right window corner while the files are loading, and then renew
the
> > normal window size some time later, the entrance picture "Design
Explorer
> > 99 SE" does not close, although the database has been opened in the
> > background. No way to make it disappear. You have to close the
application
> > completely and start it anew (and keep the window open during file
loading
> > time).
> >
> > Not really serious, but a bug.
> >
> > Regards,
> >
> > Gisbert Auge
> >

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Tony Karavidas

I see it too:

Windows 2000, SP2 on an AMD 900MHz system with a Geforce2MX card.

Tony


> Hi,
>
> I just noticed a bug which was new to me so far.
>
> If you open Protel and click on the little "minimize window" button in the
> upper right window corner while the files are loading, and then renew the
> normal window size some time later, the entrance picture "Design Explorer
> 99 SE" does not close, although the database has been opened in the
> background. No way to make it disappear. You have to close the application
> completely and start it anew (and keep the window open during file loading
> time).
>
> Not really serious, but a bug.
>
> Regards,
>
> Gisbert Auge
>

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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Cliff Lawrence

I can also confirm this bug (Win NT4.0, 2000 Protel SP6)
Cliff Lawrence

-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: 17 July 2001 13:40
To: Protel EDA Forum
Subject: [PEDA] Bug when opening Protel


Hi,

I just noticed a bug which was new to me so far.

If you open Protel and click on the little "minimize window" button in the
upper right window corner while the files are loading, and then renew the
normal window size some time later, the entrance picture "Design Explorer
99 SE" does not close, although the database has been opened in the
background. No way to make it disappear. You have to close the application
completely and start it anew (and keep the window open during file loading
time).

Not really serious, but a bug.

Regards,

Gisbert Auge


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Re: [PEDA] Bug when opening Protel

2001-07-17 Thread HxEngr
 


Re: [PEDA] Bug when opening Protel

2001-07-17 Thread Ian Wilson

On 02:40 PM 17/07/2001 +0200, [EMAIL PROTECTED] said:
>Hi,
>
>I just noticed a bug which was new to me so far.
>
>If you open Protel and click on the little "minimize window" button in the
>upper right window corner while the files are loading, and then renew the
>normal window size some time later, the entrance picture "Design Explorer
>99 SE" does not close, although the database has been opened in the
>background. No way to make it disappear. You have to close the application
>completely and start it anew (and keep the window open during file loading
>time).
>
>Not really serious, but a bug.
>
>Regards,
>
>Gisbert Auge

So that how this happens! - I have seen it a couple of times and wondered 
what the sequence is.  Makes sense - since Protel can take a long time to 
start I would often minimize it and do something else while all the 
documents re-open.  I think I will add this to the bug database as it is 
irritating and it is good to know what the cause is.

Thanks,
Ian Wilson

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[PEDA] Bug when opening Protel

2001-07-17 Thread ga

Hi,

I just noticed a bug which was new to me so far.

If you open Protel and click on the little "minimize window" button in the
upper right window corner while the files are loading, and then renew the
normal window size some time later, the entrance picture "Design Explorer
99 SE" does not close, although the database has been opened in the
background. No way to make it disappear. You have to close the application
completely and start it anew (and keep the window open during file loading
time).

Not really serious, but a bug.

Regards,

Gisbert Auge


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Re: [PEDA] Bug in design manager?

2001-05-07 Thread Dwight Harm

I can recreate the bug (99SEsp6 on Win98).  It can be done by opening a 'normal' sch 
lib (doesn't have to be a generated project
lib), change & save a part, do Update Schematic.  Then close the schematic (as you 
said, no prompt occurs) and its DDB.  Re-open and
the changes are gone.

However, there is a quicker way to correct the situation -- after re-opening, do 
"Design | Update parts in Cache".

It looks like you already reported this to Protel... maybe it'll be in SP7. :)

Dwight.

-Original Message-
From: Coleman, Tim [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, April 10, 2001 9:30 AM
To: Support (E-mail)
Cc: Protel EDA user group Forum (E-mail)
Hi,

Little problem. Looks like a bug.

Using 99SE with SP6 on an NT4 machine.

To reproduce this 'bug'.
In the schematic editor, generate a project library and then edit a part in
the library editor, update the schematic with the modified part and shutdown
the project. As the project closes you are prompted to save the library file
but not the schematic and when you re-open the project the schematic changes
have not been saved. Trying to update the schematic again from the library
editor doesn't work unless you open a propertise box on some part of the
modified symbol and close it again, then update will work. The problem is
that the schematic can be changed but the design manager does not prompt the
user to save the schematic.

Tim Coleman
Crompton Instruments
Witham
Essex
UK


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[PEDA] Bug in design manager?

2001-05-07 Thread Coleman, Tim

Hi,

Little problem. Looks like a bug.

Using 99SE with SP6 on an NT4 machine.

To reproduce this 'bug'.
In the schematic editor, generate a project library and then edit a part in
the library editor, update the schematic with the modified part and shutdown
the project. As the project closes you are prompted to save the library file
but not the schematic and when you re-open the project the schematic changes
have not been saved. Trying to update the schematic again from the library
editor doesn't work unless you open a propertise box on some part of the
modified symbol and close it again, then update will work. The problem is
that the schematic can be changed but the design manager does not prompt the
user to save the schematic.


Tim Coleman
Crompton Instruments
Witham
Essex
UK





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Re: [PEDA] Bug in design manager?

2001-05-07 Thread Fabian Hartery

I have seen stuff like this happen before. I think the fix is, you have to
save your library changes first. Then, you have to delete schematic library
settings and reinstate them. I believe this has something to do with the
embedded library structure Protel uses.

Fabe
Guigne International Limited
Paradise, Newfoundland

-Original Message-
From: Coleman, Tim [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, April 10, 2001 2:00 PM
To: Support (E-mail)
Cc: Protel EDA user group Forum (E-mail); Bricknell, Tony; Eccleston,
Barry; Lagden, Russell; Tarpey, Bob
Subject: [PEDA] Bug in design manager?


Hi,

Little problem. Looks like a bug.

Using 99SE with SP6 on an NT4 machine.

To reproduce this 'bug'.
In the schematic editor, generate a project library and then edit a part in
the library editor, update the schematic with the modified part and shutdown
the project. As the project closes you are prompted to save the library file
but not the schematic and when you re-open the project the schematic changes
have not been saved. Trying to update the schematic again from the library
editor doesn't work unless you open a propertise box on some part of the
modified symbol and close it again, then update will work. The problem is
that the schematic can be changed but the design manager does not prompt the
user to save the schematic.


Tim Coleman
Crompton Instruments
Witham
Essex
UK






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Re: [PEDA] Bug - Move Selection

2001-05-07 Thread Darren Moore



> 
> > I seem to recall flipping layers with the 'L' key (didn't it used to be
> the
> > 'S' key in the dim distant past?) and having no problems.  Does anyone
> have
> > a P98 installation running that would allow them to check what happens
> when
> > you swap to the other layer a big selection?  Are there any P99
> (non-SE -
> > though I can't see why one would) users out there that could test it.
> >
> > Ian Wilson
>
> The 'S' key was used with AdvPcb 2.8, but I am pretty sure that
> the 'L' key
> has been used instead for all succeeding versions.

The 'S' key has no effect on moving selections with 2.8, but will
flip a component. Also the 'L' key in these operations brings up
the layer dialog box.

Darren Moore

> I still use Protel 98 some of the time (inspecting legacy PCBs, and making
> minor modifications to these), and tried moving the entire contents of a
> "real world" PCB using the 'L' key. I was not that surprised that the
> outcome of doing that was once again a pig's breakfast. (I don't
> have a copy
> of AdvPcb 2.8, so I am not in a position to comment on what
> happens when the
> 'S' key is used with selected items.)


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Re: [PEDA] Bug - Move Selection (and flipping layers) SP6

2001-05-07 Thread Abd ul-Rahman Lomax

At 03:32 PM 4/6/01 +1000, Geoff Harland wrote:

>That is all very well, but text information is lost when you create Gerber
>files and then import them back into Protel again (on a different layer);
>each letter within each string gets converted into strokes (within the
>Gerber files), and as such, gets converted into "non-text" material. If I
>were to then create Acrobat files from such a PCB file, other users would
>not be able to search for R104 (say) on the Assembly drawing page(s) while
>using Acrobat's (text) searching feature

This is correct. If you want more than graphics, the gerber import method I 
use would be less than satisfactory.

However, this is a case where it would not be difficult to write a server 
or utility that would place text strings as needed on the mech layer of 
choice, from the relevant overlay layer.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433


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Re: [PEDA] Bug - Move Selection

2001-05-07 Thread Geoff Harland


> I seem to recall flipping layers with the 'L' key (didn't it used to be
the
> 'S' key in the dim distant past?) and having no problems.  Does anyone
have
> a P98 installation running that would allow them to check what happens
when
> you swap to the other layer a big selection?  Are there any P99 (non-SE -
> though I can't see why one would) users out there that could test it.
>
> Ian Wilson

The 'S' key was used with AdvPcb 2.8, but I am pretty sure that the 'L' key
has been used instead for all succeeding versions.

I still use Protel 98 some of the time (inspecting legacy PCBs, and making
minor modifications to these), and tried moving the entire contents of a
"real world" PCB using the 'L' key. I was not that surprised that the
outcome of doing that was once again a pig's breakfast. (I don't have a copy
of AdvPcb 2.8, so I am not in a position to comment on what happens when the
'S' key is used with selected items.)

Protel 98 also has the same problem of "undoing" moved polygons (polygons
that are *not* repoured are not "unmoved" properly during a following "undo"
command, and polygons that *are* repoured get repoured *again* during a
following "undo" command, rather than being "un-repoured").

My gut feeling about the 'L' key is that Protel assigns a certain amount of
"resources" for executing a layer-flipping operation. If the items being
flipped are within that limit, the outcome won't necessarily match what the
user might have been hoping for, but it won't be a pig's breakfast either.
If that limit *is* exceeded though, then werid things start happening...

The moral of the story, as I pointed out in my previous post (on this
thread), is that the 'L' key should be used with care. I honestly believe
that Protel did not envisage that users would attempt to flip/invert large
numbers of items (or entire PCB files) using this key. Quite frankly, it was
previously my belief that it was to be used *solely* for flipping one
component at a time, and until another member of this forum pointed it out,
I was unaware that this key could *also* be used to flip primitive items
residing on layers of a "paired" nature, and/or *multiple* components.

If Protel was to "fix" the 'L' key (in Protel 99 SE), what exactly would
this "fix" consist of? That said, I believe that whatever *does* happen
following the invocation of this key *should* be totally (and exactly)
undone if the user then invokes the "undo" command. But while that may not
sound unreasonable, "undoing" moved polygons properly is no small task, and
although that is a separate bug (in that it also occurs in circumstances
when the 'L' key is *not* used), fixing that would still be a constituent
part of fully "fixing" the 'L' key.

For the time being, giving the problems associated with moving polygons,
there is a lot to be said for saving a PCB file before doing so. That way,
if you don't like the outcome, you can at least then close the PCB file
(without saving it first), and then repoen it again.

Regards,
Geoff Harland.
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Re: [PEDA] Bug - Move Selection (and flipping layers) SP6

2001-05-07 Thread Abd ul-Rahman Lomax

At 12:49 PM 4/6/01 +1000, Geoff Harland wrote:

>However, I have been requested by fellow employees to create Acrobat files
>in which the pages of Assembly printouts (also) contain searchable text.
>("There are umpteen hundred components installed on this PCB. Now, exactly
>where on the PCB is component R104 installed? ...") To achieve this, I
>select the option (provided by the Power Print Server) of using *Windows*
>fonts rather than *Protel* fonts. However, as I have reported previously,
>both to this forum and directly to Protel, text strings can be displaced
>(from their actual locations) within the resulting *actual* printouts,
>*unless* the printout is of a mirrored nature. This means mirroring the
>entire PCB file to produce (acceptable) Top side Assembly printouts.
>(Arrrgh!!) :(

I do bottom assembly drawings by making mirrored bottom padmaster and 
bottom legend gerber photoplots and then importing them to an assembly 
drawing layer. I also do this with the top assembly, and I then have top 
and bottom assembly drawings side-by-side on a single assembly drawing. 
(The top assembly is typically co-located with the actual PCB.) It's nice 
that Protel allows pads on mech layers

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433


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Re: [PEDA] Bug - Move Selection (and flipping layers) SP6

2001-05-07 Thread Aalt Lokhorst

Ian Wrote:
> I should have been more explicit and anticipated this.  Redrawing the
> screen does not help. The tracks are not displayed. In fact if you know
> where one is you can double click and bring up its properties.  If you
then
> change its layer (to any other layer) it will then display correctly.
>
> The error is some sort of incomplete iteration of the linked lists or
> whatever in the display routines, at least this is what it looks like.
>
> Ian

Hello Ian,

Now I understand what you mean.

I see the 'hooroo' greeting as long as i can remember so i was wondering how
it was possible that such an Protel expert did not know about the redraw
'End' key. I should know better before answering with this response.

Sorry


Aalt Lokhorst (e-mail [EMAIL PROTECTED])

address:
  Schut Geometrische Meettechniek bv
  Duinkerkenstraat 21
  9723 BN  Groningen, The Netherlands
  tel. +31 50-5877877
  fax. +31 50-5877899





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Re: [PEDA] Bug - Move Selection (and flipping layers) SP6

2001-05-07 Thread Ian Wilson

On 09:50 AM 6/04/2001 +0200, Aalt Lokhorst said:
>Ian Wrote:
>Hello Ian,
>
>Now I understand what you mean.
>
>I see the 'hooroo' greeting as long as i can remember so i was wondering how
>it was possible that such an Protel expert did not know about the redraw
>'End' key. I should know better before answering with this response.
>
>Sorry
>
>
>Aalt Lokhorst (e-mail [EMAIL PROTECTED])

Aalt,

I hope I did not come over as rude.

Must be time for me to leave this list then (he says only half joking) - or 
at least shut-up a bit (definitely not joking).

I have quite a deep distrust of experts; in my experience a 
non-insignificant proportion of them have forgotten how to learn new 
things. This is particularly so of those that call themselves experts.  Any 
this is OT so I will toss in a Protelism.

I seem to recall flipping layers with the 'L' key (didn't it used to be the 
'S' key in the dim distant past?) and having no problems.  Does anyone have 
a P98 installation running that would allow them to check what happens when 
you swap to the other layer a big selection?  Are there any P99 (non-SE - 
though I can't see why one would) users out there that could test it.

hooroo,
Ian


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