You wrote on 11.05.2004 02:53:44:
>how does protel 99SE handle drilled slots?
not at all, unfortunately
Gisbert
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/le
Ray,
try to draw a "closed track" on the bottom layer surrounding the area you
don't want routes, and give the track the attribute "keepout". With this,
no route on bottom layer may cross this area. It may happen, that the
router places short traces which stay only within this area. Anyway, you
c
>so does the Electra router do fan outs that are nice so that you
>don't have to do them manually?
>Dennis Saputelli
Dennis,
Actually the ELECTRA router did a cleaner job of fanning out than Spectra. We used
the same "do" file to test both routers. The objective was to place vias on grid, an
to set in Spectra.
>
> Mike Reagan
>
> -Original Message-
> From: Emanuel Zimmermann [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, January 21, 2004 11:03 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Antwort: Antwort: Autorouter
>
> Mike
>
> Thanks for
EDA Forum
Subject: Re: [PEDA] Antwort: Antwort: Autorouter
Mike
Thanks for this detailed answer. It seems that I have to try the "classes
trick" to get design rules easier to specctra. I was not aware of this -
currently we work with manually edited .rul files.
Emanuel
Mike
Thanks for this detailed answer. It seems that I have to try the "classes
trick" to get design rules easier to specctra. I was not aware of this -
currently we work with manually edited .rul files.
Emanuel
---
MPL AG www.mpl.ch
Emanuel Zimmermann [E
Emanuel
We also suspect Protel is at fault for the 28 mil holes. I think it is a default in
Protel setup.
As far as High Speed design rules, You will need to stick with spectra for now, since
Electra does not support differential pairs of matched lengths. I did not try blind
and buried vias
Mike and Dennis,
As I see it the .dsn and .rte file do not contain via hole size
information cause it's not needed for autorouting. So the 28 mil hole size
is Protels bug ignoring the preference settings in the design rules while
importing and just assuming the (historically) standard 28 mil ho
Yes
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Michael Biggs
we never were off, JaMi. Must be a problem on your side.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
"JaMi Smith"
Sent: Friday, September 26, 2003 4:44 AM
Subject: [PEDA] Antwort: Silver Immersion, was: Trace Width Charts
Brian,
we went completely away from gold, nothing but problems in the soldering
process. Silver showed much better results for us. The price is about the
same. Maybe it depends on the assembl
& silver?
_
Brian Guralnick
[EMAIL PROTECTED]
- Original Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, September 26, 2003 4:44 AM
Subject: [PEDA] Antwort: Silver Immersion, was: Trace Width Charts
Brian,
we went com
Brian,
we went completely away from gold, nothing but problems in the soldering
process. Silver showed much better results for us. The price is about the
same. Maybe it depends on the assembly house and the processes they are
using.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
ww
Hi,
SPECCTRA V7 works fine with Protel99SE. Just the usual small problem with
via hole size, when read back to Protel. All via holes are set to 28mil,
need to be gloablly changed after. This issue has been between SPECCTRA and
Protel ever since, and still exists in DXP.
Mit freundlichem Gruß
Kin
>Gisbert,
>
>OK, I'm lost, call me dumb, what's a "STRG key" ?
>
>JaMi
JaMi,
Strg is written on the key on my (german) keyboard. Maybe on a us keyboard
it is named differently, "Control", may be.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
* * * * * * * * *
57 - 99
E-Mail : mailto:[EMAIL PROTECTED]
Web: <http://www.baumerident.com/>
> -Original Message-
> From: Emanuel Zimmermann [mailto:[EMAIL PROTECTED]]
> Sent: Friday, January 31, 2003 8:59 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Antwort: 99SE start failure
&
003 10:46 AM
To: Protel EDA Forum
Cc: JaMi Smith
Subject: Re: [PEDA] Antwort: 99SE start failure
Gisbert,
OK, I'm lost, call me dumb, what's a "STRG key" ?
JaMi
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROT
rotel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, January 30, 2003 1:47 PM
Subject: Re: [PEDA] Antwort: 99SE start failure
> The strange key off course. You don't have one? Well...how odd...
>
> > From: JaMi Smith [mailto:[EMAIL PROTECTED]]
&g
The strange key off course. You don't have one? Well...how odd...
> From: JaMi Smith [mailto:[EMAIL PROTECTED]]
>
> Gisbert,
>
> OK, I'm lost, call me dumb, what's a "STRG key" ?
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To lea
mith [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, January 30, 2003 10:46 AM
> To: Protel EDA Forum
> Cc: JaMi Smith
> Subject: Re: [PEDA] Antwort: 99SE start failure
>
>
> Gisbert,
>
> OK, I'm lost, call me dumb, what's a "STRG key" ?
>
> JaMi
Gisbert,
OK, I'm lost, call me dumb, what's a "STRG key" ?
JaMi
- Original Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, January 30, 2003 6:08 AM
Subject: [PEDA] Antwort: 99SE start failure
R
Rene,
while starting up 99SE hold the STRG key pressed in order to prevent 99SE
to load any project. Then load the manually one after the other to see
where the problem is located.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> this also happens when you update a schematic part from library.
>
aaah, thanks!! that is quite probably what happened with the first one.
Now the question is, does Protel consider this a bug?
Julian
--
Julian Higginson - Design Enginee
Hi Julian,
this also happens when you update a schematic part from library.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
"Julian
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
"Robert M.
Wolfe" An: "Protel EDA Forum"
<[EMAIL PROTECTED]>
Thema: Re: [PEDA] Antwort: Rules
and PCB library definitions
al Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, December 12, 2002 4:18 AM
Subject: [PEDA] Antwort: Rules and PCB library definitions
>
> Hi,
>
> I posted the attached message on this forum some days ago, but go
Hi,
I posted the attached message on this forum some days ago, but got no
reponse. Perhaps someone could try to confirm this effect. If it is not a
mistake on my side, it is a very serious bug. I would be grateful if
someone could check if this behaviour also shows under DXP. I just received
my c
Hi Dave,
if you ever renamed layers in the layer stack manager you get these strange
results. It is a bug I reported some months ago.
If you remember how to rename them to their original names, that might
help. If not, no chance (to my knowledge). Maybe a copy of layer by layer
to a clean databas
Waldemar,
I remember a similar situation. You could try two approaches:
1. save the DDB in spite of the error messages, close it. and do a "repair
" on this DDB. This helped me in one case.
2. Create a new DDB, and copy all documents from the DDB with the error
message into the new one, and then
Could we all please shift board shop and assembly house stuff to OT forum,
please?
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
* Tracking #: 4C1667C89593DA48BAA066D475531289CF70D896
*
*
Good point! However M$ has loads of resources and it might be easier for
them to support both at the same time.
> -Original Message-
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> Sent: Friday, August 30, 2002 5:15 AM
> To: Protel EDA Forum
> Subject: [PEDA] A
JaMi,
I support your views on another service pack. There are several long-known
bugs, which should be fixed as far as possible. M$ still delivers service
packs for Win2K, although Win XP is the product sold today. Altium should
do the same.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.
Hello JaMi,
the effect you describe
>This time, however, rather than wait for Protel to load, I hit the
>"minimize" button while it still has its little Protel "Logo Box" in the
>center of the screen, and is starting to load files, and it dissappears
into
>the taskbar, so I can launch PowerDesk
ot of playing around in.
Hasn't happened in any of my actual designs.
Cheers,
Gareth de Mar.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 28 August 2002 1:54
To: Protel EDA Forum
Subject: [PEDA] Antwort: 99SE Crashes when trying to close desi
Hi Matt,
press the Control Key STRG when launching Protel. That should prevent it
from loading the last document or DDB.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Tony,
you wrote on 23.07.2002 04:47:57:
>Speaking about the ability of "any other Windows Application": I really
HATE
>IT when I'm working on a document in MS Word and I decide to change my
print
>driver for HP Laserjet to Acrobat and all my FRICKIN' PAGE FORMATTING
>CHANGES!! You what that to
Thanks! I'll have to try 'print all documents' again.
Jeff Adolphs
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 16, 2002 11:40 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort: pdf output
PDF Writer works fine with schem
PDF Writer works fine with schematic 'print all documents'. It is not
necessary to sort the pages manually after printing.
Regards,
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
e-
> From: DUTTON Phil [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 4 July 2002 10:08 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Antwort: Images and Schematic Templates
>
>
> Yes, the important thing here, is that the object on your template
> always points to a def
Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 3 July 2002 18:02
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort: Images and Schematic Templates
I have been following this thread (and others on the same topic before)
with some astonishment. I placed a .TIF file with
I have to agree with Gisbert, we simply place the logo in one spot and
leave it there...it has always worked properly.
I too scratch my head at the problems reported with it. All I can say is
use a full path.
-Frank
At 10:31 AM 7/3/2002 +0200, Gisbert Auge wrote:
>I have been following this
I have been following this thread (and others on the same topic before)
with some astonishment. I placed a .TIF file with our company logo on the
schematic templates long time ago, which is stored in only one location,
far away from any protel files, and it just works fine with any project I
have
David,
I cannot support your experience. I am just doing a board containing routes
using arcs on different layers, and the print preview works just fine.
Protel 99 SE SP6, Win2K SP2.
Gisbert Auge
Hi,
use one pin and name it like you suggested. Even though double pin numbers
would probably work, it makes the schematic less readable in my view. For
example, I have been doing some designs with Motorola MPC8260 lately, which
has some 120+ port pins with up to 4 different programmable functio
Steve and Heiko,
thank you for the advice. Maybe I should have provided more details. Before
posting the question, I had checked the menu properties, and they seem to
be ok (including the ampersand at the correct position of the string). I
have W2K pro SP2 installed, and Protel SP6. Perhaps Heik
Kiernan,
>I'm still on my first PCB under P99SE. I need to add quite a few extra
routes,
>but the PCB is really dense. Can I route these on the InternalPlane
layers?
As the following text shows that you are talking about plane layers, I
would strongly discourage you to do so, though it technica
Rene,
>The update design has spurious errors. It may happen that changing
>a string ( 10k to 100k) in the schematic, leads to a hole bunch
>of actions during update design. Quite often remove a connection
>and redo the same connection. This appears to be some propagated
>errors. The probability
On 08:55 AM 15/03/2002 +0100, [EMAIL PROTECTED] said:
>I don't know of any fix, but this also is a known, old bug. Is it on the
>bug list already, Ian and Abdul?
>
>Regards,
>
>Gisbert
No not yet...
If someone wants to fill make a really nice cut-and-pastable summary I will
add it.
To really
I don't know of any fix, but this also is a known, old bug. Is it on the
bug list already, Ian and Abdul?
Regards,
Gisbert
"rimas"
Ian, resident bug librarian, please note, this one is not in the bug database:
At 10:15 AM 3/8/2002 +0100, [EMAIL PROTECTED] wrote:
>Abd ul-Rahman wrote on 07.03.2002 23:06:08:
>
> >I find that sometimes the wrong library gets removed I've reported the
> >bug, but Protel wanted more informat
Abd ul-Rahman wrote on 07.03.2002 23:06:08:
>I find that sometimes the wrong library gets removed I've reported the
>bug, but Protel wanted more information and I never got a Round Tuit.
This can be reproduced quite easily when several (more than 4 or 5)
libraries are loaded. It has been a
JaMi,
I spend about 20 - 30 minutes a day with this list; maybe more, if I decide
to write detailed posts, which seldom happens. It is really worth the time.
The members of this group are giving professional support to all kinds of
problems related to this EDA product I earn my salary with. Prob
I don't think there is. This would be on my wishlist, though.
Regards,
Gisbert
"Sean James"
Probably the solution to your proble, is to uncheck the "unrouted net
constraint" button in Tools/Design Rule Check menu, as long as the board
has not been routed. Unrouted nets are always flagged the way you describe.
This is very helpful when checking for remaining (partially) unrouted nets,
or
At 05:36 PM 2/13/2002 -0500, Andrew Jenkins wrote:
>On 06:00 PM 2/13/2002 +0100, [EMAIL PROTECTED] wrote:
> >If this is supposed to be joke, it is not funny.
> >How did the attachment slip through the Techserv filter?
>
>Because the image was embedded into the document. Considering that yours
>is
If this is supposed to be joke, it is not funny.
How did the attachment slip through the Techserv filter?
Gisbert
"Ken Henrich"
Again something I was not aware of so far. Thank you.
Gisbert
"Terry Harris"
Hi Jeff,
I know this might be of little help, but you should seriously think about
changing PLD development tools. You got the Altera tools, so why don't you
use them? There sure is a reason for most of us Protel users, as far as I
know, not to use the PLD tools from Protel. MAX Plus is freeware
According to Altium Germany the additional license fee is EUR 3875, which
is significantly cheaper than 3995 US$, if you take into account the
exchange rate, and it includes ATS and update to Phoenix. Sounds
interesting to me.
Regards,
Gisbert Auge
N.A.T. GmbH
Why don't you generate 2 sets of Gerber files, one with and one without
tenting, and select the top soldermask with tented vias from one set, and
the bottom soldermask with not tented vias from the other set?
Gisbert Auge
Hi Gene,
just keep in mind that the dongle drivers for V7 do not run under WIN2K
(and probably not under XP either). There is no known workaround for that.
No problems under W95 and W98.
Regards,
Gisbert Auge
N.A.T. GmbH
You wrote on 17.01.2002 14:43:05:
>Georg,
>
>I had a similar problem, if I understand your question correctly. We have
a
>product that used to use ispLSI2064 devices, and then we could only get
the
>2064A variant. Our programming software wouldn't work with it, as it
>detected the wrong signatur
Hi,
I can only warn you to use "standard" footprints without thorough check.
Many of them are just useless without modification and should only be taken
as examples. E.g. almost all QFP footprints have much too wide pads, and
all DSUB and RJ connectors look nice, but do most probably not match t
onix Inc.
website: www.bagotronix.com
- Original Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, December 14, 2001 4:01 AM
Subject: Re: [PEDA] Antwort: Antwort: Altera and other
>
> Hello Mark,
>
> we use Latti
"intellasys"
i-net.net>Kopie:
Thema: Re: [PED
Brian,
So, you agree that it's alright for these companies to recover their
investments by charging for the software tools and not just for the IC's.
When I bought into the Magnum, it was about $7K/seat with a $1.5K annual
fee. I have found Altera's support to be lacking, and I have long given u
Though the compiling tools for Xilinx & Altera cost money, I must admit that
there is a ton of work involved within the development of these tools. As an
example, Altera's Quartus takes my mess of gates, logic & VHDL numbering in the
million range, mushes them together, simplifies it down to
Gisbert,
You make some nice products where your work. I couldn't zoom in enough to
see what parts your using. I own the Lattice, Xilinx and Altera tools.
None were free. Used Actel at one point. It also was not free. So, who's
free tools are you using and what devices can they target?
Mar
Hallo Waldemar,
if it still is possible to go back one step to the PCB with the components
to be deleted, I would suggest that you do so. Then, in PCB editor, select
Tools/Unroute/Components and unroute the components you want to be deleted.
Then do the update PCB from Schematic. There should be
It sure does, Brian. :-)
Gisbert
"Brian
Guralnick"
You are invited to have a look at them under www.nateurope.com.
By the way, do you have a name, intellasys?
Gisbert
"intellasys"
Maybe that you can setup design rules to allow 0 or less clearance to
keepouts. During layout you have to uncheck these rules in the DRC setup
to ignore them. Then check it for the DRC.
But be careful, such practices are very dangerous! And, like Gisbert I'm
wondering the reason for this.
Emanue
Not to my knowledge, but why would you want to do that?
Gisbert Auge
N.A.T. GmbH
"Sean James"
Is why I use Atmel Uc's the assembler IDE is free, and a 2k limited C
compiler from IAR is free too :o)
Regards,
Kat.
/"\ ASCII Ribbon Campaign |K.A.Q. Electronics
\ / - NO HTML/RTF in e-mail | Software an
You wrote on 12.12.2001 10:15:02:
>Bastards... Do they want to sell ICs or software? It always makes me
>mad.
>
>Rant off... goodnight..
>
>Tony
Both, Tony, ICs and SW. Therefore, whereever possible, I implement only
devices into my designs which supply development software for free.
Gisbert
You wrote on 06.12.2001 06:36:49:
> Altium tech support is nearly irrelevant
>right now, since this forum is extremely helpful. The last time I used
>Protel support was in 1996, when I first started using the program. I
>haven't needed it since. I am quite sure that I would still need it if
>
Hi,
there is a small program called "CTSPD"
(ftp://ftp.heise.de/pub/ct/ctsi/ctspd092.zip) that does conformity and
plausibility checks on the EEPROM contents of SDRAM modules. If a module
fails this check, it does not necessarily mean that it is not working
properly, but that the EEPROM data ana
not to can the reply be posted so the rest of
us
might benefit from the recommended router settings? My other question
here,
is why wouldn't the reply have been posted here in the first place?
Mike
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Monday
I can back that statement, Abd ul-Rahman. Last week I received a mail
directed only to me from Protel support concerning the setup of the router.
I had not turned to them directly; they had been reading my postings on
this thread.
Regards,
Gisbert Auge
N.A.T. GmbH
[EMAIL PROTECTED] wrote:
> Steve,
>
> same here. Even medium designs won't route and end up with an "unable to
> initialise". Does anyone know a reason and workaround for this effect?
A couple well-known, but not well documented things. The most
important is to have a keepout border around all
At 12:36 PM 11/19/01 -0500, [EMAIL PROTECTED] wrote:
>I think what Mr Lomax was doing was trying to find a way for our unilingual
>cousins to the South to remember what antwort means, not it's literal
>translation.
No, I was speculating on what was cognate to what. wort = word is actually
better
10:12 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
> For English speakers to remember this, Ant = back, as in anterior, and
> wort, I would guess, not knowing German, would be the same as English
> "ward." S
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
> For English speakers to remember this, Ant = back, as in anterior, and
> wort, I would guess, not knowing German, would be the same as English
> "ward." So, "backward."
Not *completely* correct, though near to it.
The german "wort" is the same a
At 09:15 AM 11/19/01 +0100, [EMAIL PROTECTED] wrote:
>"Antwort" is filled in automatically by the mail tool and means "reply" in
>German language.
For English speakers to remember this, Ant = back, as in anterior, and
wort, I would guess, not knowing German, would be the same as English
"ward.
> same here. Even medium designs won't route and end up with an "unable to
> initialise". Does anyone know a reason and workaround for this effect?
I have found this to usually be due to components outside the keepout area
or the keepout area being incomplete or inside out.
The other thing th
I am using SPECCTRA for almost all boards I route, but I will gladly admit
that Mike got a point there. SPECCTRA is very powerful, but a pain in the
neck to setup and configure (pages of .do files to write, . ). I am
always looking for a program which got the DWIT button, but did not find it
Hi,
my use of Protel is
> - Schematic yes
> - PCB yes
> - Powerprint no
> - CAM Manager yes
> - Simulator no
> - Autorouter seldom
> - 3D Viewer no
> - PLD no
> - Arrange Components no
> - Autoplacer no, much worse than AR
> -
g.uk> Kopie:
Gesendet von: Thema: Re: [PEDA] Antwort: Autorouter
"Steve
"Bagotronix Tech
Support" An: "Protel EDA Forum"
<[EMAIL PROTECTED]>
Hi Ivan,
It means "Answer"
Max
-Original Message-
From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 16, 2001 9:32 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort: Autorouter
Hey, what does "Antwort" mean in the subject line o
On Fri, 16 Nov 2001, Tim Fifield wrote:
> Ivan,
> I'm also interested in what button you push.
Same here. I've got Specctra, so I don't care so much about the ARs
inability, but I've just convinced a customer of mine to buy Protel so
they can do their own maintenance of the board I've just don
Ivan,
I'm also interested in what button you push.
Tim.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 16, 2001 11:29 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort: Autorouter
Ivan,
what buttons do you push, i.e. what rules di
Protel needs to fix this too.
Best regards,
Ivan Baggett
Bagotronix Inc.
website: http://www.bagotronix.com
- Original Message -
From: <[EMAIL PROTECTED]>
To: Protel EDA Forum <[EMAIL PROTECTED]>
Sent: Friday, November 16, 2001 10:29 AM
Subject: Re: [PEDA] Antwort: Autoroute
Ivan,
what buttons do you push, i.e. what rules did you find significant playing
around with? Just being curious ...
Regards,
Gisbert Auge
N.A.T. GmbH
"Ba
Hi Tim,
we route large designs with SPECCTRA.
Gisbert Auge
N.A.T. GmbH
"Tim Fifield"
Wow, thank you, Colin, I did not know about this feature, and it's smart.
Regards,
Gisbert Auge
N.A.T. GmbH
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.ht
works also fine in Protel.
G. Auge
"Sean James"
1 - 100 of 125 matches
Mail list logo
