Re: [PEDA] Schematic Title Block - Please Explain
There is a special string for 'doc_file_name_no_path'. This is what i prefer on my templates. Have a great day Duane Thx, just what I have been looking for. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
From memory it was a JPEG image. It worked a lot better when it was converted to a .BMP Cheers, Mark Harrison Bionic Ear Institute Careful, this can change from printer driver to printer driver. IE: in my case, a postscript driver would work good, but with my laser printer in HP mode, it would completely mess up. The .jpg issue is related to jpeg's background color setting which differs from paint package to paint package. If you need a hi-res logo in the MB with a .bmp you get the color/blanks area wrong color chunks, try loading then saving you logo in an alternate paint software. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Message to Altium !!!
Good luck - Original Message - From: Peder K. Hellegaard [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Tuesday, October 12, 2004 5:10 PM Subject: [PEDA] Message to Altium !!! I am a user of P99SE and I would like to upgrade to DXP2004..BUT NOT UNTIL YOU REINTRODUCE THE GLOBAL CHANGE OPTIONS AS IN P99SE. Peder * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Message to Altium !!!
I'd guess you would call that an Altium_makem? Cheers Harry -Original Message- From: Peder K. Hellegaard [mailto:[EMAIL PROTECTED] Sent: Wednesday, October 13, 2004 7:11 AM To: [EMAIL PROTECTED] Subject: [PEDA] Message to Altium !!! I am a user of P99SE and I would like to upgrade to DXP2004..BUT NOT UNTIL YOU REINTRODUCE THE GLOBAL CHANGE OPTIONS AS IN P99SE. Peder * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Message to Altium !!!
Joe Sapienza wrote: Good luck You said it. The poster may have better luck e-mailing directly to Altium. Screaming in a private forum is not going to get much results. It will not even make it to the intended audience. Hamid - Original Message - From: Peder K. Hellegaard [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Tuesday, October 12, 2004 5:10 PM Subject: [PEDA] Message to Altium !!! I am a user of P99SE and I would like to upgrade to DXP2004..BUT NOT UNTIL YOU REINTRODUCE THE GLOBAL CHANGE OPTIONS AS IN P99SE. Peder * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Message to Altium !!!
At 02:44 PM 10/12/2004, you wrote: Joe Sapienza wrote: Good luck You said it. The poster may have better luck e-mailing directly to Altium. Screaming in a private forum is not going to get much results. It will not even make it to the intended audience. Hamid Hamid, Since you brought it up, I thought you should know that these forums enjoy a rather large Altium audience. Altium subscribers include those from the lowest ranks to the very top. You won't get an Altium response on this forum but you'll surly be heard. Forum Administrator Association of Protel EDA Users [EMAIL PROTECTED] http://www.techservinc.com/protelusers * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Message to Altium !!!
On 07:46 AM 13/10/2004, Peder K. Hellegaard said: Thank you Joe. However, I have no problems sticking with P99SE - Altium need the money more than I need DXP. They have made absolutely no improvements to their core capabilities: PCB routing. Peder, Why do you want to change to DXP2004 then? (You mentioned that you would like to upgrade in your first message in the thread, as long as they restored the old globals.) Ian Wilson I am a user of P99SE and I would like to upgrade to DXP2004..BUT NOT UNTIL YOU REINTRODUCE THE GLOBAL CHANGE OPTIONS AS IN P99SE. Peder * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Flex do's and don'ts ?
i am doing my first flex circuit other than 'talk to my fabricator' (which i am doing except for language and time zone issues) is there any such thing as a standard material callout for thickness? or a unit of incrementing the requested thickness ? something comparable to the good old 062 050 031 callouts ? our requirement is 'pretty thin, but not too thin' :} (i.e. no particular dimensional requirement) also i wonder how to call out the copper thickness i want that 'pretty thick' it will be made in China, so i guess it will be metric units i am trying to stay with normal materials and ranges so we don't ask for more than we need it will be plated through and needs to take a pretty sharp bend radius i sort of remember reading once that trace turns (corners) should be radiused is this true? anyone have a compendium of do's and don'ts ? the fabricator says they do 2.6 mil traces standard and up to 7 layers odd layer counts ok ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com Forum Administrator wrote: At 02:44 PM 10/12/2004, you wrote: Joe Sapienza wrote: Good luck You said it. The poster may have better luck e-mailing directly to Altium. Screaming in a private forum is not going to get much results. It will not even make it to the intended audience. Hamid Hamid, Since you brought it up, I thought you should know that these forums enjoy a rather large Altium audience. Altium subscribers include those from the lowest ranks to the very top. You won't get an Altium response on this forum but you'll surly be heard. Forum Administrator Association of Protel EDA Users [EMAIL PROTECTED] http://www.techservinc.com/protelusers * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
There is a special string for 'doc_file_name_no_path'. This is what i prefer on my templates. Have a great day Duane -Original Message- From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] Sent: Thursday, October 07, 2004 10:48 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Title Block - Please Explain While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC _ This e-mail has been scanned for viruses by MCI's Internet Managed Scanning Services - powered by MessageLabs. For further information visit http://www.mci.com --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE=20HTML=20PUBLIC=20-//W3C//DTD=20HTML=203.2//EN HTML HEAD META=20HTTP-EQUIV=3DContent-Type=20CONTENT=3Dtext/html;=20 charset=3Dus= -ascii META=20NAME=3DGenerator=20CONTENT=3DMS=20Exchange=20Server =20version=20= 6.5.7036.0 TITLESchematic=20Title=20Block=20-=20Please=20Explain/TITLE /HEAD BODY !--=20Converted=20from=20text/rtf=20format=20-- P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= Hi=20all,/FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= I/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D en-usFONT= =20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG =3Den-us= /SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial m=20having=20= trouble=20wrapping=20my=20head=20around=20the=20Schematic=20ti tle=20block=20= in=2099SE./FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= I=20don/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LA NG=3Den-us= FONT=20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN= 20LANG=3Den= -us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3D Arialt=20h= ave=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LAN G=3Den-us= =20FONT=20SIZE=3D2=20FACE=3DArial#8216;/FONT/SPANSPA N=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3 DArialDef= aul/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D en-usFON= T=20SIZE=3D2=20FACE=3DArialt/FONT/SPANSPAN=20LANG=3De n-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20t emplate/FON= T/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us FONT=20SIZE= =3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den- us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20fil e=20loaded=20= (under=20Tools-gt;Preferences)./FONT/SPANSPAN=20LANG=3D en-us/SPA= NSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial This=20setti= ng=20gives=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPA N=20LANG=3D= en-us=20FONT=20SIZE=3D2=20FACE=3DArialsimple/FONT/SPA NSPAN=20LA= NG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20 FACE=3DAria= l=20title=20block/FONT/SPANSPAN=20LANG=3Den-us/SPAN SPAN=20LAN= G=3Den-usFONT=20SIZE=3D2=20FACE=3DArial/FONT/SPANS PAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FA CE=3DArial= with=20no=20graphics=20etc.=20Nice,=20I/FONT/SPANSPAN=20 LANG=3Den
Re: [PEDA] Schematic Title Block - Please Explain
Terry, The simplest way is to use the ANSI title block. It is slightly larger than the standard. The ANSI does not have the extra text strings such as .DOC_FILE_NAME, or .DOC_FILE_NAME_NO_PATH So you will have to add them in. ANSI works for all sheet sizes. If it is too big, then you will neet to create the template for each sheet size. Much like the other replys stated. Rick -Original Message- From: Terry Creer [mailto:[EMAIL PROTECTED] Sent: Thursday, October 07, 2004 7:21 PM To: 'Protel EDA Forum' Subject: [PEDA] Schematic Title Block - Please Explain This is a multi-part message in MIME format. --=_NextPartTM-000-58042338-c6ad-48bd-9fa3-eb235d3429b6 Content-Type: multipart/alternative; boundary==_NextPart_000_001C_01C4AD2D.08FA9530 --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE HTML PUBLIC -//W3C//DTD HTML 3.2//EN HTML HEAD META HTTP-EQUIV=3DContent-Type CONTENT=3Dtext/html; = charset=3Dus-ascii META NAME=3DGenerator CONTENT=3DMS Exchange Server version = 6.5.7036.0 TITLESchematic Title Block - Please Explain/TITLE /HEAD BODY !-- Converted from text/rtf format -- P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 FACE=3DArialHi = all,/FONT/SPAN/P P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialI/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialm having trouble wrapping my head around the Schematic = title block in 99SE./FONT/SPAN/P P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 FACE=3DArialI = don/FONT/SPANSPAN LANG=3Den-us/SPANSPAN LANG=3Den-usFONT = SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialt have a/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArial#8216;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialDefaul/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArialt/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial template/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial file loaded (under = Tools-gt;Preferences)./FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArialThis setting gives = a/FONT/SPANSPAN LANG=3Den-us/SPANSPAN LANG=3Den-us FONT = SIZE=3D2 FACE=3DArialsimple/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial title block/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArialwith no graphics etc. = Nice, I/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialm happy/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArial#8211;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial except for one thing/FONT/SPANSPAN =
Re: [PEDA] Schematic Title Block - Please Explain
Yeh, but watch out what you replace the logo with - I once replaced it with my own logo, which looked nice on the screen, but randomly screwed up printing. It took weeks to make the connection between changing the logo and discovering why wires and labels were occasionally moving all over the printed pages! From memory it was a JPEG image. It worked a lot better when it was converted to a .BMP Cheers, Mark Harrison Bionic Ear Institute -Original Message- From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] Sent: Friday, October 08, 2004 3:48 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Title Block - Please Explain While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
Ugh, Sorry about the garbled crap - Office keeps insisting on HTML messages - should be fixed now... TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
The title block is stored in the sheet template. The sheet templates are in xx\Design Explorer 99SE\System\Templates.ddb Open a template, edit the desired elements, save the result as a .dot file with a file name of your choosing, then reuse it anytime as the template for your own custom sheet. If you change the template on-the-fly you can save as .dot file and reuse it. Yes - you have to have a separate template for each size sheet you commonly use. At 07:20 PM 10/7/04, you wrote: Hi all, Im having trouble wrapping my head around the Schematic title block in 99SE. I dont have a Default template file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, Im happy except for one thing the filename has its full path displayed and more often than not extends into and way past the Drawn By box. The other nice thing about this title block is that I can go into Document Options and change the template size and the title block always stays in the bottom right-hand corner. So my first question is where is this title block stored so I can modify it (if possible)? Now when I load a Default Template from Tools - Preferences it has the big Protel logo with Protels full address etc, etc on it. I dont remember working for Protel At least I dont think I do These templates are no good to me. These are the ones in the Templates.ddb. I realize I can generate my own template, but that brings up another problem resizing the sheet on the fly. If I use a custom template and change its size with Document Options, then the title block stays where it is (it doesnt stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is is a custom template for every sheet size I use the only way? All I want is the standard template without the full file path displayed in it. Is this asking too much? Sorry about the longwinded spiel, but I think this is important and its been bugging me for a long time. Thanks in advance for any guidance, TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC _ This e-mail has been scanned for viruses by MCI's Internet Managed Scanning Services - powered by MessageLabs. For further information visit http://www.mci.com --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE=20HTML=20PUBLIC=20-//W3C//DTD=20HTML=203.2//EN HTML HEAD META=20HTTP-EQUIV=3DContent-Type=20CONTENT=3Dtext/html;=20charset=3Dus= -ascii META=20NAME=3DGenerator=20CONTENT=3DMS=20Exchange=20Server=20version=20= 6.5.7036.0 TITLESchematic=20Title=20Block=20-=20Please=20Explain/TITLE /HEAD BODY !--=20Converted=20from=20text/rtf=20format=20-- P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= Hi=20all,/FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= I/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT= =20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den-us= /SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialm=20having=20= trouble=20wrapping=20my=20head=20around=20the=20Schematic=20title=20block=20= in=2099SE./FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= I=20don/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us= FONT=20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den= -us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialt=20h= ave=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us= =20FONT=20SIZE=3D2=20FACE=3DArial#8216;/FONT/SPANSPAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialDef= aul/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFON= T=20SIZE=3D2=20FACE=3DArialt/FONT/SPANSPAN=20LANG=3Den-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20template/FON= T/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE= =3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20file=20loaded=20= (under=20Tools-gt;Preferences)./FONT/SPANSPAN=20LANG=3Den-us/SPA= NSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArialThis=20setti= ng=20gives=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D= en-us=20FONT=20SIZE=3D2=20FACE=3DArialsimple/FONT/SPANSPAN=20LA= NG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DAria= l=20title=20block/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LAN= G=3Den-usFONT=20SIZE=3D2=20FACE=3DArial/FONT/SPANSPAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial= with=20no=20graphics=20etc.=20Nice,=20I/FONT/SPANSPAN=20LANG=3Den-u= s/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial#8217;= /FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20= SIZE=3D2=20FACE=3DArialm=20happy/FONT/SPANSPAN=20LANG=3Den-us/= SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial#8211;/= FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20S= IZE=3D2=20FACE=3DArial=20except=20for=20one=20thing/FONT/SPANSPAN=20= LANG=3Den-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3D= Arial#8211;/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D=
Re: [PEDA] CORE THICKNESSES
is there a table of standard core thicknesses somewhere? i have a 6 layer stackup top prepreg sig core gnd prepreg pwr core sig prepreg bott and am trying to hit 062 overall thickness within +-005 what are all the material thickness possibilities out there? (well maybe not ALL of them :) ) given 007 prepreg and 021 cores my vendor tells me that once you add the copper thickness at 1oz the overall is about 071 thick sounds like 017 cores would do it, but that also sounds like a wierd number thanks for any help Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CORE THICKNESSES
The standard thickness of core material depends on who makes the laminates used by your fab. If your fab can't make the board to your required dimensions, you need to call around and see what other fabs can get/do. An example of available material from one laminate manufacturer can be seen at: http://www.chemitalic.dk/content/articles/dfmmatsel.htm A table of available laminates can be seen in design guidelines from a fab at: http://www.tru-lon.co.uk/pdf/guidelines.pdf Finished thickness for prepreg and some cores can be different from the raw thickness as supplied. When heated and pressed in the laminating press, some reduction in thickness of the individual layers tends to occur. The data sheet from the laminate manufacturer gives the raw and finished thicknesses. Again, the best source of information is from the fab. If you're controlling impedance, the finished thickness data is essential for modeling stripline and microstrip characteristics. At 11:56 AM 10/3/04, you wrote: is there a table of standard core thicknesses somewhere? i have a 6 layer stackup top prepreg sig core gnd prepreg pwr core sig prepreg bott and am trying to hit 062 overall thickness within +-005 what are all the material thickness possibilities out there? (well maybe not ALL of them :) ) given 007 prepreg and 021 cores my vendor tells me that once you add the copper thickness at 1oz the overall is about 071 thick sounds like 017 cores would do it, but that also sounds like a wierd number thanks for any help Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CORE THICKNESSES
If you're trying to control impedances and PCB thickness across multiple layers, the best solution is to describe your constraints to any good fab house and ask them what they recommend. Note that fab houses can usually adjust trace widths fairly easily but adjusting center-to-center spacing is not something they do easily, if at all. Therefore, on differential traces you need to use a distinct trace width. For example, you can tell the board house which layers contain differential pairs, that you want to run them on 0.25mm, or 0.3mm center-to-center spacing with a minimum line-to-line clearance of .15mm, and that the differential impedance needs to be 62 Ohms. Then ask them what layer stackup, trace width, and center-to-center spacing they recommend. They will come back to you with a good approach. Then in the documentation give them the flexibility to adjust differential trace widths, identify the differential traces by a distinct width, tell them that width, and give them the responsibility of matching the differential impedance spec. If you are not matching any impedances, you are still better off asking them what stackup they would recommend, because you may not know what brands of material they use or regularly stock. Jeff Condit - Original Message - From: H. Selfridge [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, October 03, 2004 1:04 PM Subject: Re: [PEDA] CORE THICKNESSES The standard thickness of core material depends on who makes the laminates used by your fab. If your fab can't make the board to your required dimensions, you need to call around and see what other fabs can get/do. An example of available material from one laminate manufacturer can be seen at: http://www.chemitalic.dk/content/articles/dfmmatsel.htm A table of available laminates can be seen in design guidelines from a fab at: http://www.tru-lon.co.uk/pdf/guidelines.pdf Finished thickness for prepreg and some cores can be different from the raw thickness as supplied. When heated and pressed in the laminating press, some reduction in thickness of the individual layers tends to occur. The data sheet from the laminate manufacturer gives the raw and finished thicknesses. Again, the best source of information is from the fab. If you're controlling impedance, the finished thickness data is essential for modeling stripline and microstrip characteristics. At 11:56 AM 10/3/04, you wrote: is there a table of standard core thicknesses somewhere? i have a 6 layer stackup top prepreg sig core gnd prepreg pwr core sig prepreg bott and am trying to hit 062 overall thickness within +-005 what are all the material thickness possibilities out there? (well maybe not ALL of them :) ) given 007 prepreg and 021 cores my vendor tells me that once you add the copper thickness at 1oz the overall is about 071 thick sounds like 017 cores would do it, but that also sounds like a wierd number thanks for any help Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CORE THICKNESSES
thanks Harry Jeff the guidlines were good i am not doing impedance control, and they show more thicknesses than i had imagined - glad i'm not a fab shop! looks like i can pick one that will be plenty close and run that by my fab now that i am not just picking numbers out of the air Dennis Saputelli H. Selfridge wrote: The standard thickness of core material depends on who makes the laminates used by your fab. If your fab can't make the board to your required dimensions, you need to call around and see what other fabs can get/do. An example of available material from one laminate manufacturer can be seen at: http://www.chemitalic.dk/content/articles/dfmmatsel.htm A table of available laminates can be seen in design guidelines from a fab at: http://www.tru-lon.co.uk/pdf/guidelines.pdf Finished thickness for prepreg and some cores can be different from the raw thickness as supplied. When heated and pressed in the laminating press, some reduction in thickness of the individual layers tends to occur. The data sheet from the laminate manufacturer gives the raw and finished thicknesses. Again, the best source of information is from the fab. If you're controlling impedance, the finished thickness data is essential for modeling stripline and microstrip characteristics. At 11:56 AM 10/3/04, you wrote: is there a table of standard core thicknesses somewhere? i have a 6 layer stackup top prepreg sig core gnd prepreg pwr core sig prepreg bott and am trying to hit 062 overall thickness within +-005 what are all the material thickness possibilities out there? (well maybe not ALL of them :) ) given 007 prepreg and 021 cores my vendor tells me that once you add the copper thickness at 1oz the overall is about 071 thick sounds like 017 cores would do it, but that also sounds like a wierd number thanks for any help Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
Will do. Look for something late next week. -Original Message- From: Jeff Condit [mailto:[EMAIL PROTECTED] Sent: Thursday, September 30, 2004 9:56 AM To: Protel EDA Forum Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. AJ, Let us know your evaluation when done. I'd be interested. Thanks, Jeff Condit - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, September 29, 2004 5:28 AM Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. As is, I downloaded the demo and will give it a try. If it does what it says, the price is reasonable, and as Brian said, it has that classic flowchart feel/look... The viso comment was from my experience with Visio years ago (mid 90s). Maybe it's gotten better, but once upon a time, clunker would have been a complimentary terms, at least from me. Thanks for the info and link. aj -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Um... John, Please tell me Visio was a tongue-in-cheek suggestion... Hi aj Er no, Visio was actually a serious suggestion ;-) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP and FPGAs
Please follow up to the group as to how you resolve this problem. Sorry I can't be of any help. Bob Stephens -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Wednesday, September 29, 2004 10:55 AM To: Protel EDA Forum Subject: [PEDA] DXP and FPGAs We have DXP with all of the options except IP processors, including fpga support, but no Nanoboard. My need is to build simple logic block replacement fpgas, and insert them into pcb designs. The current fpga is an Altera EPM3128A. Made it through the schematic and pcb phases, including a schematic of the fpga functions. I was under the impression that at this point DXP would use the fpga schematic to generate a VHDL file that I could compile with the appropriate Altera software. When I go to ToolsConvertGenerate VHDL From Part, andclick on thefpga symbol in the schematic, it generates a VHDL file with only entries for the control signal pins. My call to phone support ended with the explanation that the user is supposed to fill in the details of the logic in this VHDL file and compile it manually. The examples in the manual (using the Nanoboard) certainly indicate that there is some sort of automatic file and compilation going on. Am I missing more than just the physical Nanoboard, like additional software? If DXP won't generate the VHDL file from the fpga schematic, what is the point of generating it in the first place? It seems that I could just start with the Altera software. Any help would be seriously appreciated. Stan L-Band Systems * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP and FPGAs
[EMAIL PROTECTED] wrote: We have DXP with all of the options except IP processors, including fpga support, but no Nanoboard. My need is to build simple logic block replacement fpgas, and insert them into pcb designs. The current fpga is an Altera EPM3128A. Made it through the schematic and pcb phases, including a schematic of the fpga functions. I was under the impression that at this point DXP would use the fpga schematic to generate a VHDL file that I could compile with the appropriate Altera software. When I go to ToolsConvertGenerate VHDL From Part, andclick on thefpga symbol in the schematic, it generates a VHDL file with only entries for the control signal pins. My call to phone support ended with the explanation that the user is supposed to fill in the details of the logic in this VHDL file and compile it manually. The examples in the manual (using the Nanoboard) certainly indicate that there is some sort of automatic file and compilation going on. Am I missing more than just the physical Nanoboard, like additional software? If DXP won't generate the VHDL file from the fpga schematic, what is the point of generating it in the first place? It seems that I could just start with the Altera software. Any help would be seriously appreciated. I can't help with DXP specific info, but I have done this with P99SE. You ouput a netlist from the schematic, and select VHDL as the net list format. (I had to massage the netlist a little bit to make it compatible with Xilinx's VHDL compiler, but I did get it to work. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP and FPGAs
I have never tried to use the lower level schematic components (ie mux, counter, gates, etc.) in an FPGA design. I _think_ you are supposed to be able to compile such a schematic representation and generate an fpga programming file. (however I have never used it in this way, and may be misinformed about it's abilities in this area...). I do not believe it can generate a VHDL description from a schematic representation. Except as you have described, as a higher level entity outline that you must fill in with the actual VHDL description. The real advantage is the ability to take a VHDL description, and automagically (using the FPGA to PCB wizard) have it create the complete fpga's schematic sheet, label the schematic sheet with all of the net symbols (based on the VHDL entity description), add all of the off sheet ports required, wire up the fpga's pins/ports, and to manage any future I/O pin changes as the fpga (or PCB) development matures, and pass pin changes down to the PCB. ---Phil slbsc We have DXP with all of the options except IP processors, including fpga slbsc support, but no Nanoboard. My need is to build simple logic block slbsc replacement fpgas, and insert them into pcb designs. The current fpga is slbsc an Altera EPM3128A. slbsc Made it through the schematic and pcb phases, including a schematic of the slbsc fpga functions. slbsc I was under the impression that at this point DXP would use the fpga slbsc schematic to generate a VHDL file that I could compile with the appropriate slbsc Altera software. When I go to ToolsConvertGenerate VHDL From Part, slbsc andclick on thefpga symbol in the schematic, it generates a VHDL file with slbsc only entries for the control signal pins. slbsc My call to phone support ended with the explanation that the user is slbsc supposed to fill in the details of the logic in this VHDL file and compile slbsc it manually. slbsc The examples in the manual (using the Nanoboard) certainly indicate that slbsc there is some sort of automatic file and compilation going on. Am I slbsc missing more than just the physical Nanoboard, like additional software? slbsc If DXP won't generate the VHDL file from the fpga schematic, what is the slbsc point of generating it in the first place? It seems that I could just slbsc start with the Altera software. slbsc Any help would be seriously appreciated. slbsc Stan slbsc L-Band Systems * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
As is, I downloaded the demo and will give it a try. If it does what it says, the price is reasonable, and as Brian said, it has that classic flowchart feel/look... The viso comment was from my experience with Visio years ago (mid 90s). Maybe it's gotten better, but once upon a time, clunker would have been a complimentary terms, at least from me. Thanks for the info and link. aj -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Um... John, Please tell me Visio was a tongue-in-cheek suggestion... Hi aj Er no, Visio was actually a serious suggestion ;-) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
-Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: 29 September 2004 13:28 To: [EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. The viso comment was from my experience with Visio years ago (mid 90s). Maybe it's gotten better, but once upon a time, clunker would have been a complimentary terms, at least from me. Aj Ok, I have only used it since 2002 version and it was not too bad, I used SmartDraw 3/4 before that (new versions speak 'MS Visio@ I believe) it was basic, but amazingly easy to use but we needed some office/ms project integration and Visio fitted the bill best, warts and all. http://www.smartdraw.com/enterprise/visio.htm is interesting reading John -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Um... John, Please tell me Visio was a tongue-in-cheek suggestion... Hi aj Er no, Visio was actually a serious suggestion ;-) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
AJ, Let us know your evaluation when done. I'd be interested. Thanks, Jeff Condit - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, September 29, 2004 5:28 AM Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. As is, I downloaded the demo and will give it a try. If it does what it says, the price is reasonable, and as Brian said, it has that classic flowchart feel/look... The viso comment was from my experience with Visio years ago (mid 90s). Maybe it's gotten better, but once upon a time, clunker would have been a complimentary terms, at least from me. Thanks for the info and link. aj -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Um... John, Please tell me Visio was a tongue-in-cheek suggestion... Hi aj Er no, Visio was actually a serious suggestion ;-) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
Thanks for the suggestions. I'm going to try S2F, it has that classic flowchart which I really like the look of. Brian Guralnick - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Monday, September 27, 2004 8:36 AM Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. Um... John, Please tell me Visio was a tongue-in-cheek suggestion... S2F looks pretty cool up front. Have you used S2F, and if so, what are your impressions with its efficacy for reverse engineering code? Is it really any good at the task? How much has to be manually cleaned up after app performs its conversion from code to ? Does it work with lower-level languages, ie, machine code and related? Any big caveats? Limitations? Unadvertised plusses? aj -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. Brian http://www.fatesoft.com/s2f/ There is always MS Visio amongst others. John -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Subject: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. To create software flowcharts, to date I've been using P99SE schematic capture. Sheet symbols basically were the functions entering the symbols revealed the sub-layer flowchart. Obviously, these schematics did nothing electrical. Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
-Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Monday, September 27, 2004 1:37 PM To: [EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. Um... John, Please tell me Visio was a tongue-in-cheek suggestion... Hi aj Er no, Visio was actually a serious suggestion ;-) S2F looks pretty cool up front. Have you used S2F, and if so, what are your impressions with its efficacy for reverse engineering code? Is it really any good at the task? How much has to be manually cleaned up after app performs its conversion from code to ? Does it work with lower-level languages, ie, machine code and related? Any big caveats? Limitations? Unadvertised plusses? Personally I do much software, my skills in that area kinda suck to be honest. But I have seen the reports from it and I managed to follow them, so it seems to do a decent enough job in the end but any caveats on how to get to that I cannot answer. The job it was used on was an embedded project and although mainly done in C it does have quite a bit of inline asm as well. But I guess the tool could not possibly be able to guess how every engineeer codes their own applications and I would further guess it may fall over a little on asm stuff inline which is processor specific. Sorry cannot clarify much more John -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. Brian http://www.fatesoft.com/s2f/ There is always MS Visio amongst others. John -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Subject: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. To create software flowcharts, to date I've been using P99SE schematic capture. Sheet symbols basically were the functions entering the symbols revealed the sub-layer flowchart. Obviously, these schematics did nothing electrical. Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
Jeff Stout wrote: How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. If you have a PostScript printer, you should be able to find, under advanced, then PostScript Options settings to mirror and print in negative. This is in the print options menu. But, I think you'll find the results pretty poor. Laser printers (and most others) have problems with the paper not tracking straight through, and the lasers have tricky optics to linearize the optical path, but it isn't perfect. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Mike Reagan wrote: Jon You are probably correct about SELECT ALL WIRES not working Try select all nets.This is was a carry over from using SPECTRA. Sorry about my memory lapse Thanks, that fixed that error message, but I still get the incomplete command with the UNSELECT CLASSS ( ) And, the board doesn't route real well with these settings, about 73% and what it has laid down binds up its ability to route the rest. This is a real simple board with 3 68-pin connectors and 65 nets. It has somewhat of a routing channel restriction, but the Protel default router was able to do 100% of it right off. (It made a hell of a mess of it, though.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
To summarize: There is no option to negative in my PDF Writer. PDF995 doesn't have a negative feature either. Terry Creer's method of changing color in the print preview is starting to work though I haven't got the exact formula yet. I also downloaded a ZAN printer driver which will capture the printer output and write same to a bitmap or tiff file. I then used Paint Shop to invert the colors. The only problem is the jaggies which I can sort of compensate for by going to 4x size then resized on output. Jeff Stout -Original Message- From: Jeff Stout [mailto:[EMAIL PROTECTED] Sent: Monday, September 27, 2004 2:12 PM To: [EMAIL PROTECTED] Subject: [PEDA] Negative Film Output How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. Any help appreciated. Jeff Stout * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
use CamTastic what? you haven't upgraded From: Jeff Stout [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: [EMAIL PROTECTED] Subject: [PEDA] Negative Film Output Date: Mon, 27 Sep 2004 14:11:49 -0500 How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. Any help appreciated. Jeff Stout _ Check out Election 2004 for up-to-date election news, plus voter tools and more! http://special.msn.com/msn/election2004.armx * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
I like the open-source program Dia for flowcharts. http://www.gnome.org/projects/dia/ A Windows version is at http://dia-installer.sourceforge.net/ The windows installer is the file: dia-setup-0.94.zip Paul -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Sunday, September 26, 2004 3:16 PM To create software flowcharts, to date I've been using P99SE schematic capture. Sheet symbols basically were the functions entering the symbols revealed the sub-layer flowchart. Obviously, these schematics did nothing electrical. Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Possible Bug in 99SE?
Hi terry I have see something like that and the reason is that i have forgot a simple space at the end of the name (when i rename component ). It show me the component in library, but when i place it in pcb it put the old version of component (the original copy). Regards E.BOBILLIER INRA UMRVP DOMAINE DE LA PRISE 35590 ST GILLES FRANCE Tel: 02 23 48 50 76 Fax: 02 23 48 50 80 Email : [EMAIL PROTECTED] -Message d'origine- De: Terry Creer [mailto:[EMAIL PROTECTED] Date: mercredi 22 septembre 2004 08:25 À: 'Protel EDA Forum' Objet: [PEDA] Possible Bug in 99SE? Hi All, I opened up an old PCB file. I wanted to modify a footprint that appeared more than one on the board. Not having the original library, I created one from the board (Design - Make Library). I modified the footprint and saved it. I then hit the Update PCB button. The PCB was updated accordingly, replacing all old instances of the footprint with my new one. Now the weird stuff happens. When I go to move any one of the newly modified parts, Protel changes it back to the footprint it was before! This seems to be an intermittent problem in fact Ive only seen it do this twice. Worst of all, its not repeatable. Has anyone else seen this strange behaviour? TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
26/09/2004 20:15:59, Brian Guralnick [EMAIL PROTECTED] wrote: working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. http://www.gnome.org/projects/dia/ gets the job done here. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
26/09/2004 20:15:59, Brian Guralnick [EMAIL PROTECTED] wrote: Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. Oops - http://dia-installer.sourceforge.net/ for the windows version. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Jon You are probably correct about SELECT ALL WIRES not working Try select all nets.This is was a carry over from using SPECTRA. Sorry about my memory lapse Mike Reagan -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED] Sent: Friday, September 24, 2004 4:20 PM To: Protel EDA Forum Subject: Re: [PEDA] Electra router Mike Reagan wrote: Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf Thanks, how come I could not find this document myself on the Electra web pages? I have tried this, and I do get different results, but still nothing good. I get two error messages from Electra about the commands in the DO file from Mike's white paper. For the line SELECT ALL WIRES Electra says unknown command. FOR THE LINE UNSELECT CLASSS ( ) I GET inclomplete command whether I use CLASSS (verbatim from white paper) or CLASS. (I'm still using Protel 99SE, if that makes any difference.) Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Jon Forgot to addI am not on a PC that allows me to test what I wrote. Mike Reagan -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED] Sent: Friday, September 24, 2004 4:20 PM To: Protel EDA Forum Subject: Re: [PEDA] Electra router Mike Reagan wrote: Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf Thanks, how come I could not find this document myself on the Electra web pages? I have tried this, and I do get different results, but still nothing good. I get two error messages from Electra about the commands in the DO file from Mike's white paper. For the line SELECT ALL WIRES Electra says unknown command. FOR THE LINE UNSELECT CLASSS ( ) I GET inclomplete command whether I use CLASSS (verbatim from white paper) or CLASS. (I'm still using Protel 99SE, if that makes any difference.) Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
when you setup to output the gerbers the option to invert the outputs is there just check the box - Original Message - From: Jeff Stout [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Monday, September 27, 2004 3:11 PM Subject: [PEDA] Negative Film Output How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. Any help appreciated. Jeff Stout * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
If you want it to do it in the Print Preview, without messing about with Gerbers, do the following: 1). On an unused mechanical layer, create a fill that covers the entire PCB design. 2). Create a Print preview, as per normal. 3). Choose Full Colour for your print. 4). In the preferences click the colours tab and make the Top / Bottom Layers and Multilayers WHITE. 5). Make the via and pad holes BLACK 6). Make the Mechanical Fill BLACK 7). Do your prints with the mechanical fill at the bottom, and move the orders of the layers as suits you. I used to go (From the top): Multilayer, Top/Bottom Copper, Mechanical fill. Unfortunately, there is no 'simple' way to do this, but my way works. Good luck! TC -Original Message- From: Joe Sapienza [mailto:[EMAIL PROTECTED] Sent: Tuesday, 28 September 2004 10:30 AM To: Protel EDA Forum Subject: Re: [PEDA] Negative Film Output when you setup to output the gerbers the option to invert the outputs is there just check the box - Original Message - From: Jeff Stout [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Monday, September 27, 2004 3:11 PM Subject: [PEDA] Negative Film Output How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. Any help appreciated. Jeff Stout * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
On 05:11 AM 28/09/2004, Jeff Stout said: How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. I thought PDF writers used a postscript printer driver. I thought all (most maybe) postscript printer drivers had the option of mirroring output and making it negative. Look in the Advanced dialog of the printer properties page. If you don't have access to these settings in the PDF writer you are using, you could try installing another postscript printer (connect it to the FILE: device), printing to file (as a PS file) and then using Acrobat or Ghostscript to print to transperancy. (The mirroring is useful, depending on what layer you are printing, to ensure the ink on the transparency is in contact with the light sensitive copper clad. Gives significantly better edge definition. Been more than a decade since I last made a home brew - used to have to do it on some security related stuff that the company owners did not want being sent out for commercial PCB manufacture. The camera we used was some expensive Fuji or Xerox or something - big UV thing. I remember that the gas lift hinges were wearing out and the very heavy lid would come crashing down. There was one accident prone tech who would spend time carefully lining up the film with the some cross hairs while leaning over the open camera - we would hear Owww! from the dark room as the lid came crashing down on his head.) Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
Hi Ian, We use PDF995 here and I just had a look - sure enough, under Postscript Options are the options to go Negative or Mirrored (or both). Mirrored seems to work, but Negative doesn't seem to do much... Anyone else tried it? TC -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Sent: Tuesday, 28 September 2004 11:20 AM To: Protel EDA Forum Subject: Re: [PEDA] Negative Film Output On 05:11 AM 28/09/2004, Jeff Stout said: How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. I thought PDF writers used a postscript printer driver. I thought all (most maybe) postscript printer drivers had the option of mirroring output and making it negative. Look in the Advanced dialog of the printer properties page. If you don't have access to these settings in the PDF writer you are using, you could try installing another postscript printer (connect it to the FILE: device), printing to file (as a PS file) and then using Acrobat or Ghostscript to print to transperancy. (The mirroring is useful, depending on what layer you are printing, to ensure the ink on the transparency is in contact with the light sensitive copper clad. Gives significantly better edge definition. Been more than a decade since I last made a home brew - used to have to do it on some security related stuff that the company owners did not want being sent out for commercial PCB manufacture. The camera we used was some expensive Fuji or Xerox or something - big UV thing. I remember that the gas lift hinges were wearing out and the very heavy lid would come crashing down. There was one accident prone tech who would spend time carefully lining up the film with the some cross hairs while leaning over the open camera - we would hear Owww! from the dark room as the lid came crashing down on his head.) Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
Um... John, Please tell me Visio was a tongue-in-cheek suggestion... S2F looks pretty cool up front. Have you used S2F, and if so, what are your impressions with its efficacy for reverse engineering code? Is it really any good at the task? How much has to be manually cleaned up after app performs its conversion from code to ? Does it work with lower-level languages, ie, machine code and related? Any big caveats? Limitations? Unadvertised plusses? aj -Original Message- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. Brian http://www.fatesoft.com/s2f/ There is always MS Visio amongst others. John -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Subject: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. To create software flowcharts, to date I've been using P99SE schematic capture. Sheet symbols basically were the functions entering the symbols revealed the sub-layer flowchart. Obviously, these schematics did nothing electrical. Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts.
Brian Is this any help to you? Never used it personally but it was recommended to me by someone a while back after we were requested to add flowcharts to some documentation. http://www.fatesoft.com/s2f/ There is always MS Visio amongst others. John -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Sunday, September 26, 2004 8:16 PM To: Protel EDA Forum Subject: [PEDA] Using P99SE schematic editor for creating general purpose flowcharts. To create software flowcharts, to date I've been using P99SE schematic capture. Sheet symbols basically were the functions entering the symbols revealed the sub-layer flowchart. Obviously, these schematics did nothing electrical. Now I'm working on one of my largest software projects to date, involving multiple software engineers. Should I stick with P99SE's schematic capture for my flowchart, or, is there a better utility out there designed for this particular task. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Roger, I agree the ultimate router would be set and forget like the chicken oven they advertise here in the states. But since a board aint no chicken, then routing becomes interactive. What I meant by moving in and out was selecting specific busses, route, protect these lines, then perform the same on another set of busses. Selecting lines to route in order, you are essentially setting your a routing prioritywhich is what you do manually anyway. I mentioned interactive routing in the article, I will add more to the interactive routing portions of the article. When I route large complicated boards, the actual routing time on a 3 Gig PC is only a few hours, which is insignificant to the amount of time I spend manually fanning out, addressing power distribution, and setting up design rules in Protel. Many of you out there have been screaming for a router that follows the design rules. This router follows the design rules from the native system, If you set up your design rules CORRECTLY , ELECTRA will follow it. An investment with either DXP04 or 99SE with ELECTRA and you could tackle any design. (almost any design, I am pushing the folks at ELECTRA to throw in paired wiring)Thanks for the compliment, and feel free to contact me offline if you wish I will be more than glad to help. My only interest is better tools, and sharing this knowledge with those that have educated me on this forum for the past few years, Mike Reagan EDSIwww.boarddesign.com Frederick MD -- Original Message -- From: RogerHead [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Thu, 23 Sep 2004 08:34:28 +0800 Mike, I've been following these recent posts with interest, even though I'm not (yet) an ELECTRA user. When you say 'I want to elaborate on moving in and out', what exactly do you mean? i.e. moving in and out of an Electra run (so that you can do a few things manually), or doing multiple Electra runs for selected parts of a layout, or...? The ultimate router has to be a 'start-and-forget-it' utility, but 35+ years experience tells us that it's not going to happen any time soon. Until then we need all the tips, education, and coercion to make the best use of the tools that we do have. Keep up the good work Roger At 11:01 PM 20-09-04, you wrote: Tony Thanks for the feedback. I might work on second revision because I want to elaborate on moving in and out, routing selected nets and components only. To answer your questions: Why not to use the DO file from DXP? You can set up all of your design rules inside the PCB file, almost all of the rules will be transferred seamlessly to the router dsn file. There is little need to add effort by writing a long do file. With the exception to guarantee that you wont choke off any routing paths I rarely write more than a few lines in do file. DXP and 99 do an excellent job of maintaining the design rules for the router. DXP has a slight edge with better support for classes. The Do file from DXP is not a usable file, that is why I mentioned not to use it. It can nt be tweaked, there is more information contained in the dsn file. Tweak your design rules in the pcb file. This is where it should be done anyways. I need to read what I wrote about the MAX vias.. I will respond later this morning to that question Mike Reagan -Original Message- From: Tony Karavidas [mailto:[EMAIL PROTECTED] Sent: Saturday, September 18, 2004 3:05 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Thursday, September 16, 2004 10:28 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis, On High Density designs its all about the VIAS. Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact
Re: [PEDA] Protel version 3
I did have 2.8 running on win XP for a bit just to investigate something I felt was amiss with an old file, ran inside a window, since so much work was done in the newer formats I can say I didn't have it up long enough to perform a true functional test, seemed ok for me, your mileage may vary. - Original Message - From: Website Visitor [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Friday, September 24, 2004 3:57 PM Subject: [PEDA] Protel version 3 Has anybody had any luck running version 3 on newer machines and/or windows 2000 pro? If not, what is the latest windows version will it run on? Thanks. E-mail: [EMAIL PROTECTED] Posted from Association web site by: Roger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Mike Reagan wrote: Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf Thanks, how come I could not find this document myself on the Electra web pages? I have tried this, and I do get different results, but still nothing good. I get two error messages from Electra about the commands in the DO file from Mike's white paper. For the line SELECT ALL WIRES Electra says unknown command. FOR THE LINE UNSELECT CLASSS ( ) I GET inclomplete command whether I use CLASSS (verbatim from white paper) or CLASS. (I'm still using Protel 99SE, if that makes any difference.) Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel version 3
I use version 3.5 on Win2k pro on a 3 year old Sony laptop. The only thing that I have noticed is that I have to load Protel first whenever I start up my computer. If I start anything else first and even shut that application down, Protel will not start. The problem may be elsewhere but as little as I use it, I just live with it. Jim Walker Walker Power Design, Inc. [EMAIL PROTECTED] 877 281-7483 Website Visitor wrote: Has anybody had any luck running version 3 on newer machines and/or windows 2000 pro? If not, what is the latest windows version will it run on? Thanks. E-mail: [EMAIL PROTECTED] Posted from Association web site by: Roger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel version 3
I had Protel v3 , complete configuration, running on a dual CPU machine running win 2k pro in a dual display /RAID HDD configuration . I also had Protel v3 running on a 1.5GHz Toshiba laptop with a dual screen display (the laptop lcd plus an external lcd panel) . It ran fine on both machines . I had the same Protel v3 later installed on a home machine , a weird Sony Vaio running winXP and it worked fine for the limited purpose of reviewing old designs. I never tried generating new files with the Vaio setup though. Best Regards, Matt Tudor , MSEE - Original Message - From: Website Visitor [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Friday, September 24, 2004 3:57 PM Subject: [PEDA] Protel version 3 Has anybody had any luck running version 3 on newer machines and/or windows 2000 pro? If not, what is the latest windows version will it run on? Thanks. E-mail: [EMAIL PROTECTED] Posted from Association web site by: Roger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE memory errors
Thanks Steve and Ian! I re-installed printer drivers and re-installed Protel along with deleting Protel files that do not uninstall. Everything seems to be working so far. Jeff Adolphs Lake Shore Cryotronics, Inc Westerville, OH -Original Message- From: Ian Rozowsky [mailto:[EMAIL PROTECTED] Sent: Wednesday, September 22, 2004 2:28 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Protel 99SE memory errors I've found that many of my print preview problems have been solved by re-installing the printer driver. Ian Rozowsky RD Director Centurion Systems (Pty) Ltd. Box 506 Cramerview 2060 South Africa [EMAIL PROTECTED] ||Anti-spam - please remove the ** from the e-mail address before sending|| http://www.centsys.co.za -Original Message- From: Jeff Adolphs [mailto:[EMAIL PROTECTED] Sent: 21 September, 2004 21:02 To: Protel EDA Forum (E-mail) Subject: [PEDA] Protel 99SE memory errors Hi! I am getting memory error when I click on print preview from the pcb layout. I have uninstalled Protel 99SE and reinstalled with Sevice Pack 6. I have Windows 2000 and 1/2 gig of RAM. Protel 99SE has worked well for a long time on my current machine. Could the latest Window updates be causing Protel 99SE to no longer run? Additionally I have repaired the database and still get Protel crashing. Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio - This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. Please note that any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Centurion Systems (Pty) Ltd. Finally, while Centurion Systems attempts to ensure that all email is virus-free, Centurion Systems accepts no liability for any damage caused by any virus transmitted by this email. - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Possible Bug in 99SE?
i have NEVER seen anything like that not even sure how that would be possible given that there is no cache for the PCB parts can you describe a little more about the nature of the changes and differences between old and new parts ? almost sounds like the image in memory is confused i bet if you close the file and reopen you will not be able to reproduce the problem Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Mike, I've been following these recent posts with interest, even though I'm not (yet) an ELECTRA user. When you say 'I want to elaborate on moving in and out', what exactly do you mean? i.e. moving in and out of an Electra run (so that you can do a few things manually), or doing multiple Electra runs for selected parts of a layout, or...? The ultimate router has to be a 'start-and-forget-it' utility, but 35+ years experience tells us that it's not going to happen any time soon. Until then we need all the tips, education, and coercion to make the best use of the tools that we do have. Keep up the good work Roger At 11:01 PM 20-09-04, you wrote: Tony Thanks for the feedback. I might work on second revision because I want to elaborate on moving in and out, routing selected nets and components only. To answer your questions: Why not to use the DO file from DXP? You can set up all of your design rules inside the PCB file, almost all of the rules will be transferred seamlessly to the router dsn file. There is little need to add effort by writing a long do file. With the exception to guarantee that you wont choke off any routing paths I rarely write more than a few lines in do file. DXP and 99 do an excellent job of maintaining the design rules for the router. DXP has a slight edge with better support for classes. The Do file from DXP is not a usable file, that is why I mentioned not to use it. It can nt be tweaked, there is more information contained in the dsn file. Tweak your design rules in the pcb file. This is where it should be done anyways. I need to read what I wrote about the MAX vias.. I will respond later this morning to that question Mike Reagan -Original Message- From: Tony Karavidas [mailto:[EMAIL PROTECTED] Sent: Saturday, September 18, 2004 3:05 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Thursday, September 16, 2004 10:28 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis, On High Density designs its all about the VIAS. Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Ethernet Connection
Also, match signal path lengths to minimize relative skew. Jeff Condit - Original Message - From: Jason Morgan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 22, 2004 2:48 AM Subject: Re: [PEDA] Ethernet Connection It depends on many things, but I don't think you need to use an extra internal RJ45, unless there is a manufacturing reason for it. I use internal Ethernet in all our products. You need to take into account: Ethernet speed - 10baseT and you'll probably be OK, 100Base or faster and you need to be very careful. Location of components, keep the internal Ethernet lengths as short as possible. Trace impedance - keep the trace impedance as close to 100 Ohms as possible. Discontinuity - there will be an impedance discontinuity at the connector. If its 10Base, and the components are close to the connector, and the traces are short, there should be little trouble. If its 100Base, the components are well separated, and the lines are long, then you'll probably be in trouble. Lets call the external connector board 'LEFT', and the internal electronics board 'RIGHT'. Obviously, I don't know your design, but you could mount the PHY and the magnetics on the LEFT, then use the much slower and synchronous MII to interface to the MAC on the RIGHT. In any case, always put the magnetics as close to the RJ connector as possible, use magjacks if possible. You could remove the problem by choosing an impedance matched connector, but these are much more expensive. Download Polar si8000 from their website, they do a pay-as-you-go version that will help you make sure your trace design is correct. Don't trust Protel's 'Impedance matching' in all but a few cases, its way off the mark, just compare polars 'real world models' with protels textbook generic formula and you'll see what I mean. Depending on your board construction, make use of broadside stripline or edge coupled differential traces, this will help you get the impedance you want. If you have use of a network analyser and don't think twice about sending PCBs to fab then your job is easy, just make prototypes until its right. If you have totally internal Ethernet connections, have a search for application notes on using 'transformerless' or 'capacitive' coupling between PHYs, this will save loads. Hope this all helps, Jason. -Original Message- From: Back, Norb [mailto:[EMAIL PROTECTED] Sent: 21 September 2004 19:26 To: Protel EDA Forum Subject: [PEDA] Ethernet Connection Importance: High Hi all First time for a Ethernet connection The layout calls for all out side connections (RJ-45 jack) to be on one board and mate with a mother board threw a 125 pin mating connector, down the mother bd to were a TINI bd will be mounted Or would putting another RJ-45 jack on the mother bd right next to the 125 pin connector And use a Ethernet patch cord to the TINI bd be better? The connection bd and mother bd need to be able to separate Any help or tricks Still using 99SE Thanks Norbert J Back C.I.D. Engineering Technician Gilson Inc. 3000 W. Beltline Hwy. Middleton, WI. 53562 PH 1- 800-445-7661 ex-4438 Fax 608-821-4498 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Ethernet Connection
It depends on many things, but I don't think you need to use an extra internal RJ45, unless there is a manufacturing reason for it. I use internal Ethernet in all our products. You need to take into account: Ethernet speed - 10baseT and you'll probably be OK, 100Base or faster and you need to be very careful. Location of components, keep the internal Ethernet lengths as short as possible. Trace impedance - keep the trace impedance as close to 100 Ohms as possible. Discontinuity - there will be an impedance discontinuity at the connector. If its 10Base, and the components are close to the connector, and the traces are short, there should be little trouble. If its 100Base, the components are well separated, and the lines are long, then you'll probably be in trouble. Lets call the external connector board 'LEFT', and the internal electronics board 'RIGHT'. Obviously, I don't know your design, but you could mount the PHY and the magnetics on the LEFT, then use the much slower and synchronous MII to interface to the MAC on the RIGHT. In any case, always put the magnetics as close to the RJ connector as possible, use magjacks if possible. You could remove the problem by choosing an impedance matched connector, but these are much more expensive. Download Polar si8000 from their website, they do a pay-as-you-go version that will help you make sure your trace design is correct. Don't trust Protel's 'Impedance matching' in all but a few cases, its way off the mark, just compare polars 'real world models' with protels textbook generic formula and you'll see what I mean. Depending on your board construction, make use of broadside stripline or edge coupled differential traces, this will help you get the impedance you want. If you have use of a network analyser and don't think twice about sending PCBs to fab then your job is easy, just make prototypes until its right. If you have totally internal Ethernet connections, have a search for application notes on using 'transformerless' or 'capacitive' coupling between PHYs, this will save loads. Hope this all helps, Jason. -Original Message- From: Back, Norb [mailto:[EMAIL PROTECTED] Sent: 21 September 2004 19:26 To: Protel EDA Forum Subject: [PEDA] Ethernet Connection Importance: High Hi all First time for a Ethernet connection The layout calls for all out side connections (RJ-45 jack) to be on one board and mate with a mother board threw a 125 pin mating connector, down the mother bd to were a TINI bd will be mounted Or would putting another RJ-45 jack on the mother bd right next to the 125 pin connector And use a Ethernet patch cord to the TINI bd be better? The connection bd and mother bd need to be able to separate Any help or tricks Still using 99SE Thanks Norbert J Back C.I.D. Engineering Technician Gilson Inc. 3000 W. Beltline Hwy. Middleton, WI. 53562 PH 1- 800-445-7661 ex-4438 Fax 608-821-4498 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE memory errors
Jeff Adolphs wrote: Hi! I am getting memory error when I click on print preview from the pcb layout. I have uninstalled Protel 99SE and reinstalled with Sevice Pack 6. I have Windows 2000 and 1/2 gig of RAM. Protel 99SE has worked well for a long time on my current machine. Could the latest Window updates be causing Protel 99SE to no longer run? Additionally I have repaired the database and still get Protel crashing. You might do well to run a memory test program on the computer. This doesn't sound like a software problem. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE memory errors
Jeff, Have you tried unloading and re-installing your printers? My regards, Steve Smith Staco Energy Products Co. 301 Gaddis Boulevard. Dayton, OH 45403 Telephone: (937) 253-1191 Ext. 158 Fax: (937) 253-1723 E-mail: [EMAIL PROTECTED] Web Site: www.stacoenergy.com www.stacopower.com -Original Message- From: Jeff Adolphs [mailto:[EMAIL PROTECTED] Sent: Tuesday, September 21, 2004 3:02 PM To: Protel EDA Forum (E-mail) Subject: [PEDA] Protel 99SE memory errors Hi! I am getting memory error when I click on print preview from the pcb layout. I have uninstalled Protel 99SE and reinstalled with Sevice Pack 6. I have Windows 2000 and 1/2 gig of RAM. Protel 99SE has worked well for a long time on my current machine. Could the latest Window updates be causing Protel 99SE to no longer run? Additionally I have repaired the database and still get Protel crashing. Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Tony Thanks for the feedback. I might work on second revision because I want to elaborate on moving in and out, routing selected nets and components only. To answer your questions: Why not to use the DO file from DXP? You can set up all of your design rules inside the PCB file, almost all of the rules will be transferred seamlessly to the router dsn file. There is little need to add effort by writing a long do file. With the exception to guarantee that you wont choke off any routing paths I rarely write more than a few lines in do file. DXP and 99 do an excellent job of maintaining the design rules for the router. DXP has a slight edge with better support for classes. The Do file from DXP is not a usable file, that is why I mentioned not to use it. It can nt be tweaked, there is more information contained in the dsn file. Tweak your design rules in the pcb file. This is where it should be done anyways. I need to read what I wrote about the MAX vias.. I will respond later this morning to that question Mike Reagan -Original Message- From: Tony Karavidas [mailto:[EMAIL PROTECTED] Sent: Saturday, September 18, 2004 3:05 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Thursday, September 16, 2004 10:28 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis, On High Density designs its all about the VIAS. Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Good morning, You should catch a missing parentheses on page 7 if you're going to revise your article. I couldn't get the special clearance rules to work until i added a closing parentheses to your DO file command below: rule pcb (clearance 17(type via_via) many thanks for writing this article duane -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Monday, September 20, 2004 8:01 AM To: 'Protel EDA Forum' I might work on second revision because I want to elaborate on moving in and out, routing selected nets and components only. -Original Message- From: Tony Karavidas [mailto:[EMAIL PROTECTED] Sent: Saturday, September 18, 2004 3:05 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
This is a multi-part message in MIME format. Thanks you Duane for the inputs. How did it work for you? Mike Reagan -Original Message- From: Duane Foster [mailto:[EMAIL PROTECTED] Sent: Monday, September 20, 2004 12:27 PM To: Protel EDA Forum Subject: Re: [PEDA] Electra router Good morning, You should catch a missing parentheses on page 7 if you're going to revise your article. I couldn't get the special clearance rules to work until i added a closing parentheses to your DO file command below: rule pcb (clearance 17(type via_via) many thanks for writing this article duane -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Monday, September 20, 2004 8:01 AM To: 'Protel EDA Forum' I might work on second revision because I want to elaborate on moving in and out, routing selected nets and components only. -Original Message- From: Tony Karavidas [mailto:[EMAIL PROTECTED] Sent: Saturday, September 18, 2004 3:05 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Hi Mike, It's nice to see this published. Figures 2 and 3 need to be swapped or the text needs to be swapped. One page 7, there is a sentence which doesn't make sense to me: A good rule is to use is maximum via I tried to make sense of it by continuing to read, but it didn't help. Can you explain what you mean? There is a typo on page 8. (first paragraph, second to last sentence.) How come you say not to use DXP's DO file? Does it generate bad info? Isn't it a good place to start and then manually tweek it? Doesn't DXP communicate the PCB rules into Electra through the DO file, or do the rules migrate through the DSN file? (I thought that was the board layout only) Thanks! Tony -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: Thursday, September 16, 2004 10:28 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Electra router Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis, On High Density designs its all about the VIAS. Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3D Models Online
Hey Jason, See my answers to your questions below. Q1: Is it worth doing? I've thought about the benefits of this previously. In my case however, I don't think it would be worth it. Having dealt with alot of offshore suppliers etc., we try to hedge our bets so to speak. We've been burned a few times when a plastics shooting company doesn't give the necessary clearances around components etc. As a result, when I model 3d components I generally model them as MMC + 0.4mm per side and MMC + 0.2mm height. This ensures that we get at least a minimal amount of clearance. Another issue (which could be overcome) is the level of detail of a part. For instance, I downloaded a model from Molex for their ZIF flex socket (51374) that has every feature modelled to the point where it can be opened and closed. For my purposes, this is far more detail than necessary and only slows down my CAD system. I only need the basic outer dimensions and enough detail for any mating parts (in the case of connectors etc.) It would also be far more beneficial to have the models in native CAD format rather than a generic format like .stp or .igs so that features can easily be removed or added. I typically like to set up my models so that they can be placed manually or used in an IDF conversion program. Therefore, I build them using the same reference locations as used for the part footprints in Protel. Q2: What do you think is a good price for a model of the following? I'll pass on this question for lack of experience. Q3: Would you use the service? Though I think it would be a beneficial service for some, I would prefer to keep our 3d modelling under my own control due to the uniqueness of the issues we face. However, I can see certain situations (such as a time crunch) where being able to download the model would be useful. I think the need for this service would increase if the Protel - 3d (IDF) conversions worked better (I've trialed IDF modeller, and use Qualecad, but only for Protel 99SE). Hope that helps, Darcy Davis Design Engineer, Dynastream Innovations, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Problem with grid placement of components in P99SE.
Sorry guys, Brain fade, I wasn't looking at the properties window anywhere except for the coordinate locations. I didn't notice that the properties window was defaulting to the reference designator tab and giving me the coordinates of the reference designator rather than the component. All the designators are centered and thus have some weird coordinates. Sincerely, Brad Velander, PCB Designer. Northern Airborne Technology 1925 Kirschner Road, Kelowna, BC, V1Y 4N7. (250) 763-2329 ext. 225 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis, On High Density designs its all about the VIAS. Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Routing a big PGA part
The default via pad and hole size Protel uses is rather large, a smaller via and hole size should probably be selected. The other major factors would be the routing rules for: - The spacing between the pins of the PGA socket. - The trace widths. - The clearance between the tracks and to the PGA pads. If you've calculated these and you really are out of routing channels, you probably do need to add more layers. With 200+ I/O pins, if even half of those pins are outputs, and they are switching all at the same time, or switching at high speeds, you will benefit from having Power and GND planes in other ways. Less noise, less ground bounce, better EMI, etc. Moving the GND/PWR to the planes (and the wider tracks probably supplying them) will make routing it easier. With a 200+pin PGA, I'd want (you may even need) the planes. ---Phil WV Hello, WV I am looking for some info and help on a decent routing WV scheme for a 200+ pin PGA socket. I am using only a 2 sided board WV right now, but wondering if a 4 layer layout would be best. WV Customer wants to go low cost.. WV Seems you run out of routing room from the inside pins to the WV outside ones. Not much room to drop vias in. WV I thought I might have to pull out the center pins to put in WV vias, but run into the problems again, no routing room. WV Any suggestions or visual aids? WV Thanks from a new protel99 user! WV Leif WV [EMAIL PROTECTED] WV Posted from Association web site by: Leif Erickson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
I would like to thank you all for your replies. Since we use Protel only for schematics layouts, I think that I will not recommend upgrading at this time. I will download the trial version and take a good look at it when time allows. Thanks again. Regards, Steve Smith, C.I.D. Product Engineer Staco Energy Products Co. 301 Gaddis Boulevard. Dayton, OH 45403 Web Site: www.stacoenergy.com www.stacopower.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
Steve- don't bother getting the trial till you actually have the time to do the eval because the trial will expire after 30 days even if you don't install it right away. I really hate this server activation stuff! JM At 05:21 AM 9/15/2004, you wrote: I would like to thank you all for your replies. Since we use Protel only for schematics layouts, I think that I will not recommend upgrading at this time. I will download the trial version and take a good look at it when time allows. Thanks again. Regards, Steve Smith, C.I.D. Product Engineer Staco Energy Products Co. 301 Gaddis Boulevard. Dayton, OH 45403 Web Site: www.stacoenergy.com www.stacopower.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Len I suspect you also typed route and walked away to drink your coffee while the board routed. Was this after you used the autoplacement tools? Take a deep breath, put you reading glasses on and read the article I wrote for Electra. I have no vested interest in this with Electra, (unlike some others on this list). If you follow the format I outlined, you will learn to use an autorouter.I learned from a fellow named FRANK FRANK. That is not a typo that is his both his first and last names. After attending numerous and useless canned demos and seminars with Cadence, Frank opened my eyes on how to use autorouters.Frank has also endorsed this router. I would have to say he is one of the foremost experts in autorouting I have ever met. Please dont type route and walk away from the PC again, your boss might think you can be replaced with software. It is not a matter of free speech, it is a matter of saying something that is totally wrong. Doesnt any one have any integrity anymore? The router works well. Mike Reagan -- Original Message -- From: Leonard Gabrielson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 19:55:01 -0700 So much for freedom of speech. I downloaded the Electra router, and really wanted to give it a fair shake. I was very optimistic when I started, but it didn't take long to become very, very disappointed. 99SE is far superior. Len - Original Message - From: edsi [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 13, 2004 6:04 PM Subject: Re: [PEDA] time to upgrade 99SE? / Electra router Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] time to upgrade 99SE? / Electra router
Specctra isn't a turn key product, like most Protel users expected the Protel Autorouter to be. I was always impressed how simple Protel was to use in the beginning but learning to pass parameters to the Specctra Autorouter was much more of a challenge. I have seen the output of the Specctra Autorouter in the hands of a trained 'DO file' maker. It can do very good work. It can also create garbage just as well if the 'DO Files' are in their default state. I attended a seminar on the Specctra Autorouter and see that it has many features that if known about would make the job of communicating with the software much better. Perhaps Electra is similar? Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 http://pcbwizards.com -Original Message- From: edsi [mailto:[EMAIL PROTECTED] Sent: Monday, September 13, 2004 6:05 PM To: Protel EDA Forum Subject: Re: [PEDA] time to upgrade 99SE? / Electra router Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf it is pretty interesting, exp the strategy re via to via spacing rule Dennis Saputelli edsi wrote: Len I suspect you also typed route and walked away to drink your coffee while the board routed. Was this after you used the autoplacement tools? Take a deep breath, put you reading glasses on and read the article I wrote for Electra. I have no vested interest in this with Electra, (unlike some others on this list). If you follow the format I outlined, you will learn to use an autorouter.I learned from a fellow named FRANK FRANK. That is not a typo that is his both his first and last names. After attending numerous and useless canned demos and seminars with Cadence, Frank opened my eyes on how to use autorouters.Frank has also endorsed this router. I would have to say he is one of the foremost experts in autorouting I have ever met. Please dont type route and walk away from the PC again, your boss might think you can be replaced with software. It is not a matter of free speech, it is a matter of saying something that is totally wrong. Doesnt any one have any integrity anymore? The router works well. Mike Reagan -- Original Message -- From: Leonard Gabrielson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 19:55:01 -0700 So much for freedom of speech. I downloaded the Electra router, and really wanted to give it a fair shake. I was very optimistic when I started, but it didn't take long to become very, very disappointed. 99SE is far superior. Len - Original Message - From: edsi [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 13, 2004 6:04 PM Subject: Re: [PEDA] time to upgrade 99SE? / Electra router Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] time to upgrade 99SE? / Electra router
Bill Electra and Specctra are identical in behavior and commands. The commands for each connection can be understood if you open a Protel dsn file with Wordpad. Experiment with Protel's design rules, set up layer rules, minimize vias, restrict layers, set directions etc, then review the dsn file with Wordpad. If the commands still make sense, dont conflict with each other, and you have a routing channel, Electra and Specctra will place your wire as clean or cleaner than you could draw it. It is that simple. In my article, I mentioned the amount of time I take to set up a board for routing. Very large boards can take a week to set up. This still beats months of basket weaving. I too attended the Cadence canned seminars and never learned to use the router. One day after many trials it came to me like getting baptized in Holy water. I figured out how to route. I feel confident that I can auto route the hardest or all boards a backplane with no vias, just straight connections. Row A to Row A Row B to Row B, etc.I can set up a few rules and autoroute a backplane... using Protel's design rules and net classes. If ya'll followed my postings several years ago, I didnt think this could be done. Piece of cake. Differential and matched pairs well Im working on it. Ive got diff pairs down cant get Protel to export length rules BTW there are some improvements in the DXP dsn export. Mike Reagan -- Original Message -- From: Brooks,Bill [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Tue, 14 Sep 2004 12:59:21 -0700 Specctra isn't a turn key product, like most Protel users expected the Protel Autorouter to be. I was always impressed how simple Protel was to use in the beginning but learning to pass parameters to the Specctra Autorouter was much more of a challenge. I have seen the output of the Specctra Autorouter in the hands of a trained 'DO file' maker. It can do very good work. It can also create garbage just as well if the 'DO Files' are in their default state. I attended a seminar on the Specctra Autorouter and see that it has many features that if known about would make the job of communicating with the software much better. Perhaps Electra is similar? Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 http://pcbwizards.com -Original Message- From: edsi [mailto:[EMAIL PROTECTED] Sent: Monday, September 13, 2004 6:05 PM To: Protel EDA Forum Subject: Re: [PEDA] time to upgrade 99SE? / Electra router Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] time to upgrade 99SE? / Electra router
edsi wrote: Differential and matched pairs well Im working on it. Ive got diff pairs down cant get Protel to export length rules This is interesting. Does Electra handle diff pairs well? I mean, it will zig-zag them to match? Does it also handle matched lengths, if the rules are set properly? Stephen * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cannot click pcb parts from DXP
thanks i'll look at that ds Darren wrote: Hi Dennis, Looks like the bit that selects that is in the 4th line as shown below, this is an ASCII version of the file. 1780 is the stack bit checked and 1720 is unchecked, you might be able to do a change in a text editor, but that would depend on what other bits might be set also. ENDCOMP DEFAULTS 0 0 900 1720 1 1 1 1 ENDCOMP DEFAULTS 0 0 900 1780 1 1 1 1 Not sure what the problem is with the double click looks like the component area has a problem, save to ASCII might fix that also. Just tried opening a ex-dxp file from 2004 and the pad stack enable is checked.. :( Regards, Darren Moore -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] we are working on a board which is a substantial variant of a board which was done in DXP (not in P2004) by someone else my working file was saved back to 99SE which is what we are using i notice a few anomalies and wonder if there is any comment some, but not all, components cannot be dbl clicked to edit later we discovered that dbl clicking somewhere nearby but not particularly close to the component made the edit function work what is up with that ? another thing it seems that the pads of all components all have the 'enable padstack' enabled and of course that is not one of the properties available as a global edit in 99SE does the save back to 99SE always make 'use padstack' enabled because it is the norm in DXP? i am not sure this is a problem but it was at least a curiosity for me Dennis Saputelli -- __ _ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cannot click pcb parts from DXP
when i save as ASCII in 99SE and examine the file i don't see anything like what you show below re stack i see records which are one per line and when i search the file for either 'DEFAULTS' or '1780' neither is found however saving the file as ASCII did appear to correct the component area problem so it does not look like the DXP to 99SE save back is exactly seamless Dennis Saputelli Darren wrote: Hi Dennis, Looks like the bit that selects that is in the 4th line as shown below, this is an ASCII version of the file. 1780 is the stack bit checked and 1720 is unchecked, you might be able to do a change in a text editor, but that would depend on what other bits might be set also. ENDCOMP DEFAULTS 0 0 900 1720 1 1 1 1 ENDCOMP DEFAULTS 0 0 900 1780 1 1 1 1 Not sure what the problem is with the double click looks like the component area has a problem, save to ASCII might fix that also. Just tried opening a ex-dxp file from 2004 and the pad stack enable is checked.. :( Regards, Darren Moore -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] we are working on a board which is a substantial variant of a board which was done in DXP (not in P2004) by someone else my working file was saved back to 99SE which is what we are using i notice a few anomalies and wonder if there is any comment some, but not all, components cannot be dbl clicked to edit later we discovered that dbl clicking somewhere nearby but not particularly close to the component made the edit function work what is up with that ? another thing it seems that the pads of all components all have the 'enable padstack' enabled and of course that is not one of the properties available as a global edit in 99SE does the save back to 99SE always make 'use padstack' enabled because it is the norm in DXP? i am not sure this is a problem but it was at least a curiosity for me Dennis Saputelli -- __ _ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cannot click pcb parts from DXP
from 99SE assci file here is a record of no pad stack followed by one with padstack |RECORD=Pad|COMPONENT=0|SELECTION=FALSE|LAYER=MULTILAYER|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|NAME=5|X=6760mil|Y=5980mil|XSIZE=62mil|YSIZE=62mil|SHAPE=ROUND|HOLESIZE=32mil|ROTATION=180.000|PLATED=TRUE|DAISYCHAIN=Load|CCSV=0|CPLV=0|CCWV=1|CENV=1|CAGV=1|CPEV=1|CSEV=1|CPCV=1|CPRV=1|CCW=10mil|CEN=4|CAG=10mil|CPE=0mil|CSE=4mil|CPC=20mil|CPR=20mil |RECORD=Pad|COMPONENT=0|SELECTION=FALSE|LAYER=MULTILAYER|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|NAME=6|X=6860mil|Y=5980mil|TOPXSIZE=62mil|MIDXSIZE=61mil|BOTXSIZE=62mil|YSIZE=62mil|SHAPE=ROUND|HOLESIZE=32mil|ROTATION=180.000|PLATED=TRUE|DAISYCHAIN=Load|CCSV=0|CPLV=0|CCWV=1|CENV=1|CAGV=1|CPEV=1|CSEV=1|CPCV=1|CPRV=1|CCW=10mil|CEN=4|CAG=10mil|CPE=0mil|CSE=4mil|CPC=20mil|CPR=20mil Dennis Saputelli Darren wrote: Hi Dennis, Looks like the bit that selects that is in the 4th line as shown below, this is an ASCII version of the file. 1780 is the stack bit checked and 1720 is unchecked, you might be able to do a change in a text editor, but that would depend on what other bits might be set also. ENDCOMP DEFAULTS 0 0 900 1720 1 1 1 1 ENDCOMP DEFAULTS 0 0 900 1780 1 1 1 1 Not sure what the problem is with the double click looks like the component area has a problem, save to ASCII might fix that also. Just tried opening a ex-dxp file from 2004 and the pad stack enable is checked.. :( Regards, Darren Moore -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] we are working on a board which is a substantial variant of a board which was done in DXP (not in P2004) by someone else my working file was saved back to 99SE which is what we are using i notice a few anomalies and wonder if there is any comment some, but not all, components cannot be dbl clicked to edit later we discovered that dbl clicking somewhere nearby but not particularly close to the component made the edit function work what is up with that ? another thing it seems that the pads of all components all have the 'enable padstack' enabled and of course that is not one of the properties available as a global edit in 99SE does the save back to 99SE always make 'use padstack' enabled because it is the norm in DXP? i am not sure this is a problem but it was at least a curiosity for me Dennis Saputelli -- __ _ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
There are two areas where upgrading would be a no-brainer for me. -If you are doing any multi-channel design work. -If you are doing any FPGA work. I have mixed feelings about the autorouter. The ability to define rules to drive it has been expanded and improved. But I don't think the route engine itself is quite there yet. (SP2 maybe?? :P) How well the autorouter works seems to vary some from board to board. On one board, my results were better than the 99SE router. With another board the results were not as good. I crash less often than I used to in 99SE. Noticeably fewer AV's. I wouldn't go back to 99SE. The future will be on the DXP platform. Is it perfect? Probably not. But we're only at SP1. Some growing pains are only natural. I expect DXP will just continue to improve over the next few service packs. I'd at least get the demo, have a look for yourself, try it out, see how well it works (or not..) with a few of your own designs. ---Phil SS Hi all, SS It's time for me to request equipment software for next SS years budget and I still don't have a warm fuzzy feeling about SS Protel 2004. Has SP1 improved the Situs autorouter? Are the SS other improvements worth the $3500 USD? I have seen a few of you SS say that once you had upgraded you would never go back. Is it SS really that much better or are the systems so incompatible that SS once 2004 is learned it would be tough to go back and do it the SS 99SE way, much less admit that the money was poorly spent? We SS only design about 10 boards a year and I am having a real problem SS justifying the cost of upgrading from 99SE SP6 to myself much less SS my boss. SS My regards, SS Steve Smith, C.I.D. SS Product Engineer SS Staco Energy Products Co. SS 301 Gaddis Boulevard. SS Dayton, OH 45403 SS Telephone: (937) 253-1191 Ext. 158 SS Fax: (937) 253-1723 SS E-mail: [EMAIL PROTECTED] SS Web Site: www.stacoenergy.com SS www.stacopower.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
Hi Phillip, Phillip Stevens wrote: Is it perfect? Probably not. But we're only at SP1. Some growing pains are only natural. I expect DXP will just continue to improve over the next few service packs. I would say DXP is at SP5. I would bring out major steps in quality of Protel DXP product, release times may be bit wrong, but not much: - DXP (July 2002?) - DXP SP1 (October 2002?) - DXP SP2 (December 2002?) - DXP SP3pre104 (March 2003?) - DXP 2004 (February 2004?) - DXP 2004 SP1 (June 2004?) So over 2 years of selling the product and 'growing pains are natural'. Khmm... Yeah! Right! On the other hand, I'm mostly happy with DXP, using it since September 2002. Then from time to time, now all the time. DXP has done huge leap with every SP. Indrek -- Indrek Rebane | Borthwick-Pignon Electronics Engineer|Tartu Science Park Phone: (+372) 7 302 641 | Riia 185, 51014 Tartu Fax: (+372) 7 383 041 | Estonia [EMAIL PROTECTED]| www.bps.co.ee * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
Steve Smith wrote: Hi all, It's time for me to request equipment software for next years budget and I still don't have a warm fuzzy feeling about Protel 2004. Has SP1 improved the Situs autorouter? Are the other improvements worth the $3500 USD? I have seen a few of you say that once you had upgraded you would never go back. Is it really that much better or are the systems so incompatible that once 2004 is learned it would be tough to go back and do it the 99SE way, much less admit that the money was poorly spent? We only design about 10 boards a year and I am having a real problem justifying the cost of upgrading from 99SE SP6 to myself much less my boss. 10 boards is not a measure, unless they contain less than 3 transistors and equally many passives. Before it is forgotten. You're not done with those 3500$. Put another monitor and a dual head graphics card onto the list too. Rene -- Ing.Buro R.Tschaggelar http://www.ibrtses.com Your newsgroups @ http://www.talkto.net * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
At 08:30 AM 9/13/2004, Steve Smith wrote: Hi all, It's time for me to request equipment software for next years budget and I still don't have a warm fuzzy feeling about Protel 2004. Has SP1 improved the Situs autorouter? Yes but not enough to make it useful for the boards I design (mostly high speed). I know others are using it successfully but everybody has different needs and different levels of acceptability so you'll probably need to test drive the router to really get a feel for what it can do. Are the other improvements worth the $3500 USD? If you are upgrading from a version earlier than 99se, I'd say its certainly worth the price and will give you many improvements in all areas of the software. If you are upgrading from 99se its a much tougher call. I'll direct the rest of my comments for a 99se upgrader. First, let me say my experience is the following: Most of my work is in PCB layout- probably 90%, about 9% Schematic, and maybe 1% CAM and Autorouter. I don't use the FPGA module at all. If I used PCB less and others modules more, my comments would quite different since they received more attention and improvements than PCB. I've been using DXP04 for a few months now. If I were considering the upgrade at the current price I'd pass on it till the next major upgrade in features. This is mostly because DXP04 reduces productivity by replacing easy-to-use global editing with complex queries and it offers no enhancements in high speed design. Features that are added to PCB layout do not substantially improve productivity. I have seen a few of you say that once you had upgraded you would never go back. I have seen a few of them too. I wonder how many of them can claim PCB layout as their primary job function? I may be wrong but I'd guess that they may already have one or more programing languages under their belt. This would make DXP's query based system more natural for them. Is it really that much better or are the systems so incompatible that once 2004 is learned it would be tough to go back and do it the 99SE way, much less admit that the money was poorly spent? We only design about 10 boards a year and I am having a real problem justifying the cost of upgrading from 99SE SP6 to myself much less my boss. I don't think that it's difficult to go back to 99se. On the contrary, it's difficult to return to DXP due to the more complex user interface and query language. After going from DXP to 99se for just a couple weeks I find I am forgetting much of the query structure. I really have to work at learning DXP. The learning curve is much steeper than any of the past Protel/Altium products. As I'm sure you've seen others write, DXP uses selection differently than 99se. The selection also works in conjunction with a new 'masking' feature. It's different enough from 99se that I find it very difficult to stay proficient on both systems. Also, gone is the quick and easy to use global editing replaced with overly complex text based queries. DXP also employs a 'Find Similar Object' function which was meant to replace some of the ease-of-use of global editing, but it falls short failing to match the power and simplicity of global edits. After a few months using DXP for PCB layout I'm still much slower in DXP. I know I'll get more proficient in time but I'll never match my productivity using 99se until more improvements are added to DXP. If you use more autorouting or schematic more than I do, let that be the deciding factor and give DXP a try. Then again, the cost of the upgrade and the cost of the learning curve are both steep. At just 10 boards a year you would probably be better off from the standpoint of financial cost and delivery schedule to stay with what you have. If your making equipment requests, don't forget a faster machine. My AMD3200 with 1G dual channel RAM is too slow for DXP. After cross probing to an 11 sheet schematic it takes an agonizing 12 seconds just to clear the selection and mask (guess I'll start cross-probing paper or PDF prints)! Also, you're going to want a second monitor (and maybe a bigger desk for the extra monitor). It seems accepted that DXP's plethora of panels and lists make a 2nd display necessary for efficient use. My estimate of the real cost of the DXP04 $3,500 upgrade is closer to $10,000+ after adding the hardware, hardware software installation, training, learning curve, slower design cycle, possible design errors, and more. I have a feeling that my copy of DXP will start gathering dust once my current series of designs are complete. I'll dust it off after some serious enhancements come along and I've upgraded my hardware. JM * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
On Tue, 14 Sep 2004 00:02:13 +0200, Rene Tschaggelar [EMAIL PROTECTED] wrote: Before it is forgotten. You're not done with those 3500$. Put another monitor and a dual head graphics card onto the list too. Rene which may be a good investment in itself. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004?
2004 has a completly different user interface and if you dont mind spending time some time every day looking through the knowledge base and asking questions on the forum, then go for it. I have recently upgraded but have spent lots of time just trying to figure out the interface and ways to do simple tasks in 99SE which seemed way too complicated in 2004. However it seems the promises of 99SE such as simulation, routing and signal integrity tools actually might work in 2004. But it still has cut and paste array renumbering problems (sch renumbers the array a certain way whilst pcb has a different renumbering sequence!) and poor support for differential routing. The array renumbering problems are a big issue for the types of boards I do and its enough for me to use both programs for design, but I find myself mostly using P99SE due to its easy to use and fast. Clive Rene Tschaggelar [EMAIL PROTECTED] on 09/14/2004 08:02:13 AM Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc:(bcc: Clive Broome/sdc) Subject: Re: [PEDA] Is it time to upgrade from 99SE to Protel 2004? Steve Smith wrote: Hi all, It's time for me to request equipment software for next years budget and I still don't have a warm fuzzy feeling about Protel 2004. Has SP1 improved the Situs autorouter? Are the other improvements worth the $3500 USD? I have seen a few of you say that once you had upgraded you would never go back. Is it really that much better or are the systems so incompatible that once 2004 is learned it would be tough to go back and do it the 99SE way, much less admit that the money was poorly spent? We only design about 10 boards a year and I am having a real problem justifying the cost of upgrading from 99SE SP6 to myself much less my boss. 10 boards is not a measure, unless they contain less than 3 transistors and equally many passives. Before it is forgotten. You're not done with those 3500$. Put another monitor and a dual head graphics card onto the list too. Rene -- Ing.Buro R.Tschaggelar http://www.ibrtses.com Your newsgroups @ http://www.talkto.net * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] time to upgrade 99SE? / Electra router
Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] time to upgrade 99SE? / Electra router
So much for freedom of speech. I downloaded the Electra router, and really wanted to give it a fair shake. I was very optimistic when I started, but it didn't take long to become very, very disappointed. 99SE is far superior. Len - Original Message - From: edsi [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 13, 2004 6:04 PM Subject: Re: [PEDA] time to upgrade 99SE? / Electra router Jon I dont believe for a minute that you know what you are doing. These are some pretty harsh words but dont blast a product (ELECTRA)that failed to route only becuase you dont understand how it works. If Electra didnt work then Spectra wont work either. SPECCTRA is a world class router, whose performance has not been equaled. I dont expect you could get this router to work either. The command set is the same for both routers... so SPECCTRA sucks too ...right? Learn to use the damm program before you release your ignorant opinion. Mike Reagan -- Original Message -- From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] Date: Mon, 13 Sep 2004 16:59:29 -0500 I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cannot click pcb parts from DXP
we are working on a board which is a substantial variant of a board which was done in DXP (not in P2004) by someone else my working file was saved back to 99SE which is what we are using i notice a few anomalies and wonder if there is any comment some, but not all, components cannot be dbl clicked to edit later we discovered that dbl clicking somewhere nearby but not particularly close to the component made the edit function work what is up with that ? another thing it seems that the pads of all components all have the 'enable padstack' enabled and of course that is not one of the properties available as a global edit in 99SE does the save back to 99SE always make 'use padstack' enabled because it is the norm in DXP? i am not sure this is a problem but it was at least a curiosity for me Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cannot click pcb parts from DXP
Hi Dennis, Looks like the bit that selects that is in the 4th line as shown below, this is an ASCII version of the file. 1780 is the stack bit checked and 1720 is unchecked, you might be able to do a change in a text editor, but that would depend on what other bits might be set also. ENDCOMP DEFAULTS 0 0 900 1720 1 1 1 1 ENDCOMP DEFAULTS 0 0 900 1780 1 1 1 1 Not sure what the problem is with the double click looks like the component area has a problem, save to ASCII might fix that also. Just tried opening a ex-dxp file from 2004 and the pad stack enable is checked.. :( Regards, Darren Moore -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] we are working on a board which is a substantial variant of a board which was done in DXP (not in P2004) by someone else my working file was saved back to 99SE which is what we are using i notice a few anomalies and wonder if there is any comment some, but not all, components cannot be dbl clicked to edit later we discovered that dbl clicking somewhere nearby but not particularly close to the component made the edit function work what is up with that ? another thing it seems that the pads of all components all have the 'enable padstack' enabled and of course that is not one of the properties available as a global edit in 99SE does the save back to 99SE always make 'use padstack' enabled because it is the norm in DXP? i am not sure this is a problem but it was at least a curiosity for me Dennis Saputelli -- __ _ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE Find Files Found
Dennis Saputelli wrote: by right window i meant the main right hand pane when the list of files is showing over there (and only then) I should add - not only then. I mean you don't have to have a ddb open to be able to access this feature. After you start Protel so the Design Explorer's empty window opens you may press F3 - like Windows' Find File, but it executes Protel's Find Files process. I think it's more common that one needs to find a file before any ddb is open. Regards, Wojciech Oborski * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] High Speed Design (was: 99SE Find Files Found)
Jim, I agree. Of course there are still some designs being done that aren't high speed and for which HSDD tools wouldn't help. Maybe the CEO is still imagining PCB design is what it was a decade or two ago. After all, when was the last time the CEO probably laid out a HSDD board? (Or likely any board for that matter?) Maybe what we need to do is somehow focus on convincing the CEO of the magnitude of this paradigm shift in the industry and the impact it has on overall productivity. I have spent 100's of hours balancing differential traces and serpentine busses in complex designs of high density. If it is understood how huge the need is and how common it is becoming, it should also become clear why designers without such tools cannot be competitive and so for survival must mandatorily switch to another tool. When over half the designs you do involve HSDD, you won't win any if your bid is based on twice as many hours as people with proper tools; and you can't just no bid them or arbitrarily cut your bid in half to win it: you'll go out of business. Jeff Condit - Original Message - From: Jim Monroe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, September 09, 2004 1:31 PM Subject: Re: [PEDA] High Speed Design (was: 99SE Find Files Found) Mike- that was my point. DXP has not added or improved ANY high speed design capabilities. DXP is nearly unchanged from 99se. In fact, I'd venture to say that more capability had been removed than added. The 99se high speed rules and length matching were an okay start when they were introduced many years ago, but I was expecting those features to be polished and additional capabilities to be added. That hasn't happened. Here's an abbreviated list of what I need in the realm of high speed design: * All nets and classes must have a skew length factor to compensate for the various in-chip lengths of different signals. * Length matching must support series caps and resistors. * Length matching parameters must include WIDTH (frequency?), not just gap and amplitude. * The length matching amplitude parameter must be a maximum setting (not fixed) so that the length matching can reduce amplitude as needed to fit the zig-zagging within the available space around each net. * Length matching must run in batch mode. Manually running each pass to add just one amplitude section at a time is ridiculous. Would any EDA vendor dream of making an autorouter that only partially routed each net before it had to be re-started (yeah, maybe Altium)? Ideally, the length matching would automatically regenerate (much like polygons) if a net were rerouted. * Must have design rules specific to differential pairs. * Must have Interactive routing of differential pairs (both nets are placed simultaneously with correct width and spacing per rules). I could make this list much longer but these are the basics. These features could easily save me 20-30 hours per board! There was an article recently pointed out by another forum member (sorry I don't remember who or when exactly) which seemed to indicate that Altium's CEO doesn't think high speed design features are very important (at least that was my interpretation). Given that, and the fact that DXP has added very little design capability to PCB layout, I am very rapidly loosing hope that DXP is a platform that I will be able to continue using much longer. JM At 05:59 AM 9/9/2004, Mike Reagan wrote: Jim wrote: .DXP is now moving toward it's 2nd birthday and I think most of us feel its not nearly as usable or productive as its predecessor. 99se was showing its age in it's lack of many high speed design features. Jim I would be interested in hearing one high speed feature that was implemented in DXP. I have yet to find any. I use both DXP and 99SE. If anything 99SE has a huge advantage over DXP with ease of use in the design rules menu. Try to set up maximum parallel rules between net classes in DXP sometime, it becomes an experiment in programming. Actually, I found a bug in DXP that it doesnt support more than three different levels of layer rules when exporting to a dsn file. This is hardlly a high speed advancement. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE Find Files Found
Jim wrote: .DXP is now moving toward it's 2nd birthday and I think most of us feel its not nearly as usable or productive as its predecessor. 99se was showing its age in it's lack of many high speed design features. Jim I would be interested in hearing one high speed feature that was implemented in DXP. I have yet to find any. I use both DXP and 99SE. If anything 99SE has a huge advantage over DXP with ease of use in the design rules menu. Try to set up maximum parallel rules between net classes in DXP sometime, it becomes an experiment in programming. Actually, I found a bug in DXP that it doesnt support more than three different levels of layer rules when exporting to a dsn file. This is hardlly a high speed advancement. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PEDA] 99SE Find Files Found
I either missed the first few posts or I just don't get it. Dennis wrote i just stumbled (after all this time!) on ctrl-F when in the main file list in the RIGHT window (only place it shows and which exposes the Find Files .. in the File Menu) I can't seem to figure out how to do this. He mentions the RIGHT window. Are we referring to something I don't know of? I usually only have the Design Explorer Window open and the item I am working on (ie: Schematic, PCB.) Any clarification would be appreciated. Thanks. Dan Enslen The only reason time exists is so everything doesn't happen all at once. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE Find Files Found
Yeah, it had me confused too but I finally figured it out. He means The xxx.DDB document window. You must have a database open and it'll be the left most document tab or only tab if you don't have any of the database's documents open. It's a nifty feature. JM At 08:24 AM 9/9/2004, you wrote: I either missed the first few posts or I just don't get it. Dennis wrote i just stumbled (after all this time!) on ctrl-F when in the main file list in the RIGHT window (only place it shows and which exposes the Find Files .. in the File Menu) I can't seem to figure out how to do this. He mentions the RIGHT window. Are we referring to something I don't know of? I usually only have the Design Explorer Window open and the item I am working on (ie: Schematic, PCB.) Any clarification would be appreciated. Thanks. Dan Enslen The only reason time exists is so everything doesn't happen all at once. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] High Speed Design (was: 99SE Find Files Found)
Mike- that was my point. DXP has not added or improved ANY high speed design capabilities. DXP is nearly unchanged from 99se. In fact, I'd venture to say that more capability had been removed than added. The 99se high speed rules and length matching were an okay start when they were introduced many years ago, but I was expecting those features to be polished and additional capabilities to be added. That hasn't happened. Here's an abbreviated list of what I need in the realm of high speed design: * All nets and classes must have a skew length factor to compensate for the various in-chip lengths of different signals. * Length matching must support series caps and resistors. * Length matching parameters must include WIDTH (frequency?), not just gap and amplitude. * The length matching amplitude parameter must be a maximum setting (not fixed) so that the length matching can reduce amplitude as needed to fit the zig-zagging within the available space around each net. * Length matching must run in batch mode. Manually running each pass to add just one amplitude section at a time is ridiculous. Would any EDA vendor dream of making an autorouter that only partially routed each net before it had to be re-started (yeah, maybe Altium)? Ideally, the length matching would automatically regenerate (much like polygons) if a net were rerouted. * Must have design rules specific to differential pairs. * Must have Interactive routing of differential pairs (both nets are placed simultaneously with correct width and spacing per rules). I could make this list much longer but these are the basics. These features could easily save me 20-30 hours per board! There was an article recently pointed out by another forum member (sorry I don't remember who or when exactly) which seemed to indicate that Altium's CEO doesn't think high speed design features are very important (at least that was my interpretation). Given that, and the fact that DXP has added very little design capability to PCB layout, I am very rapidly loosing hope that DXP is a platform that I will be able to continue using much longer. JM At 05:59 AM 9/9/2004, Mike Reagan wrote: Jim wrote: .DXP is now moving toward it's 2nd birthday and I think most of us feel its not nearly as usable or productive as its predecessor. 99se was showing its age in it's lack of many high speed design features. Jim I would be interested in hearing one high speed feature that was implemented in DXP. I have yet to find any. I use both DXP and 99SE. If anything 99SE has a huge advantage over DXP with ease of use in the design rules menu. Try to set up maximum parallel rules between net classes in DXP sometime, it becomes an experiment in programming. Actually, I found a bug in DXP that it doesnt support more than three different levels of layer rules when exporting to a dsn file. This is hardlly a high speed advancement. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE Find Files Found
Jim, I waited like you for 2004sp1 till I bought my copy. I found it a mighty tool but complicated to use. I´d have to agree in some of the things you wrote. Still I find P99SE easier to use and more intuitive then DXP2004_sp1. But there is one thing I have to point on. Have a Look on the download-pages on Protel.com . There are 1 service-pack for Protel99 and 6 (!) of them for 99SE. Perhaps we shall give Altium some more time? As long as they give us servicepacks free of charge there stil is hope. :-) Regards, Waldemar -Original Message- From: Jim Monroe [mailto:[EMAIL PROTECTED] Subject: Re: [PEDA] 99SE Find Files Found I'd have to agree. 99se did and still does represent the height of Protel's EDA systems. ...snipp... I think the DXP platform could have been another pinnacle but they got carried away with the new interface or perhaps the task of merging all their EDA products under a single 'easy to use' platform was just too daunting. ...snipp... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
I also changed Tools-ERC-Setup-Net Identifier Scope to 'Net Labels and Ports Global' which got rid of 16 pages of input errors and warnings flagged because they were only connected to a port symbol. Jeff Condit - Original Message - From: Jeff Condit [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 7:33 AM Subject: [PEDA] P98 SE Schematic ERC for Electrical Pin Types OK; basic question: In P98 SE, how do you configure the electrical types of pins to be input/output/power/passive/unknown etc. such that in schematic you can do such things as run an ERC and find nets that don't have an output? How exactly do you initiate such an ERC? How can you override noted conditions that are really acceptable ones such that you don't have to keep rummaging through them every time? NOTE: One of my customers masters all his schematics exclusively in Protel 98 SE using flat topology and is not about to change, so I must use it for the schematic tool in this particular case. It is not practical to convert to DXP and back for each minor change. Jeff Condit 6946 Clark Rd. Paradise, CA 95969 Office: (530) 877-6443 Cell: (530) 228-6780 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
I set the options for Unconnected Ports within the connection matrix for the 8 cells where * Port crosses Unconnected? Now ERC shows unconnected ports. Does Protel sometimes flag more than one error at the same location? If so, how can No ERC Directives correctly identify which error to not report? Is there any way to change to electrical type definition of a pin on the schematic? PLDs with hundreds of pins intrinsically designated as I/O regardless of programming give rise to a very large number of warnings, such as an IO=Output clash. If I could, for example, magically change and I/O pin to an input where applicable it would make these errors go away. However, since the same PLD part type is used in many designs with different programming, I don't want to change the pin definitions in the library. What about nets with no outputs? How can these be checked to make sure they are what is wanted? For example, when 2 boards are interconnected in a system, one could have only an output (and connector pin) while the other has only inputs (and a connector pin). Is there any way to check that Port directions make sense with regard to pin electrical types? For example, the port should point into an input and away from an output? Jeff Condit 6946 Clark Rd. Paradise, CA 95969 Office: (530) 877-6443 Cell: (530) 228-6780 [EMAIL PROTECTED] - Original Message - From: Jeff Condit [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 8:20 AM Subject: Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types I also changed Tools-ERC-Setup-Net Identifier Scope to 'Net Labels and Ports Global' which got rid of 16 pages of input errors and warnings flagged because they were only connected to a port symbol. Jeff Condit - Original Message - From: Jeff Condit [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 7:33 AM Subject: [PEDA] P98 SE Schematic ERC for Electrical Pin Types OK; basic question: In P98 SE, how do you configure the electrical types of pins to be input/output/power/passive/unknown etc. such that in schematic you can do such things as run an ERC and find nets that don't have an output? How exactly do you initiate such an ERC? How can you override noted conditions that are really acceptable ones such that you don't have to keep rummaging through them every time? NOTE: One of my customers masters all his schematics exclusively in Protel 98 SE using flat topology and is not about to change, so I must use it for the schematic tool in this particular case. It is not practical to convert to DXP and back for each minor change. Jeff Condit 6946 Clark Rd. Paradise, CA 95969 Office: (530) 877-6443 Cell: (530) 228-6780 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
You mean P99SE, yes? Or do you mean P98? Pin types are defined at the component level, and the part editors are used to define these characteristics. Once the target part has been brought into the part editor, it's simply a matter of doublwe-clicking a pin, then examining the resultant pin-edit window to determine and/or modify its electrical type. Good luck, aj -Original Message- From: Jeff Condit [mailto:[EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 10:33 AM To: Protel EDA Forum Subject: [PEDA] P98 SE Schematic ERC for Electrical Pin Types OK; basic question: In P98 SE, how do you configure the electrical types of pins to be input/output/power/passive/unknown etc. such that in schematic you can do such things as run an ERC and find nets that don't have an output? How exactly do you initiate such an ERC? How can you override noted conditions that are really acceptable ones such that you don't have to keep rummaging through them every time? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
Hi AJ! I meant P98SE. I guess what I was balking at was not being able to reconfigure a pin's electrical type from schematic. The reason is that generic PLDs don't really have an electrical type until they are programmed. Then the pins can become inputs, outputs, tri-state, or whatever you want. If in the library they are all just set to I/O, then the schematic reports a lot of warnings and can miss some errors. If you know what you want the pins to be (which is only sometimes the case) and can set the pin electrical types accordingly, then the ERC is much more meaningful. This could be done in the parts editor, but then the part would be wrong on other designs where the pins are used differently. Thus, the desire to be able to characterize them in schematic. Anyway, that was the thought. Jeff Condit - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 10:29 AM Subject: Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types You mean P99SE, yes? Or do you mean P98? Pin types are defined at the component level, and the part editors are used to define these characteristics. Once the target part has been brought into the part editor, it's simply a matter of doublwe-clicking a pin, then examining the resultant pin-edit window to determine and/or modify its electrical type. Good luck, aj -Original Message- From: Jeff Condit [mailto:[EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 10:33 AM To: Protel EDA Forum Subject: [PEDA] P98 SE Schematic ERC for Electrical Pin Types OK; basic question: In P98 SE, how do you configure the electrical types of pins to be input/output/power/passive/unknown etc. such that in schematic you can do such things as run an ERC and find nets that don't have an output? How exactly do you initiate such an ERC? How can you override noted conditions that are really acceptable ones such that you don't have to keep rummaging through them every time? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
I found the Tools-ERC menu option. I think I missed it first time around because I was not on a schematic document at the time. So this answers the portion regarding how to initiate ERC. I also found Place-Directives-No ERC which is used to mark things like unused inputs. This is helpful, but doesn't do the job an override does. Still looking for input on this subject. Thanks, Jeff Condit - Original Message - From: Jeff Condit [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 7:33 AM Subject: [PEDA] P98 SE Schematic ERC for Electrical Pin Types OK; basic question: In P98 SE, how do you configure the electrical types of pins to be input/output/power/passive/unknown etc. such that in schematic you can do such things as run an ERC and find nets that don't have an output? How exactly do you initiate such an ERC? How can you override noted conditions that are really acceptable ones such that you don't have to keep rummaging through them every time? NOTE: One of my customers masters all his schematics exclusively in Protel 98 SE using flat topology and is not about to change, so I must use it for the schematic tool in this particular case. It is not practical to convert to DXP and back for each minor change. Jeff Condit 6946 Clark Rd. Paradise, CA 95969 Office: (530) 877-6443 Cell: (530) 228-6780 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
Jeff Condit wrote: Hi AJ! I meant P98SE. I guess what I was balking at was not being able to reconfigure a pin's electrical type from schematic. The reason is that generic PLDs don't really have an electrical type until they are programmed. Then the pins can become inputs, outputs, tri-state, or whatever you want. If in the library they are all just set to I/O, then the schematic reports a lot of warnings and can miss some errors. If you know what you want the pins to be (which is only sometimes the case) and can set the pin electrical types accordingly, then the ERC is much more meaningful. This could be done in the parts editor, but then the part would be wrong on other designs where the pins are used differently. Thus, the desire to be able to characterize them in schematic. Anyway, that was the thought. Jeff Condit For large programmable parts like Altera's FPGAs, I make a special schematic symbol for each application, with the pins named and positioned (and set the the correct type) to suit the application. I find it much easier to understand the schematic with the pins named for their functions, rather than all being called I/On -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types
Thanks Peter. That's what I like to do as well, but its takes a little more time to do and the customer is not always willing to pay for it. In this particular case, the customer made it the way it is and wants it that way, so the customer gets what the customer wants. Jeff Condit - Original Message - From: Peter Bennett [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 08, 2004 2:50 PM Subject: Re: [PEDA] P98 SE Schematic ERC for Electrical Pin Types Jeff Condit wrote: Hi AJ! I meant P98SE. I guess what I was balking at was not being able to reconfigure a pin's electrical type from schematic. The reason is that generic PLDs don't really have an electrical type until they are programmed. Then the pins can become inputs, outputs, tri-state, or whatever you want. If in the library they are all just set to I/O, then the schematic reports a lot of warnings and can miss some errors. If you know what you want the pins to be (which is only sometimes the case) and can set the pin electrical types accordingly, then the ERC is much more meaningful. This could be done in the parts editor, but then the part would be wrong on other designs where the pins are used differently. Thus, the desire to be able to characterize them in schematic. Anyway, that was the thought. Jeff Condit For large programmable parts like Altera's FPGAs, I make a special schematic symbol for each application, with the pins named and positioned (and set the the correct type) to suit the application. I find it much easier to understand the schematic with the pins named for their functions, rather than all being called I/On -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE Find Files Found
i just stumbled (after all this time!) on ctrl-F when in the main file list in the RIGHT window (only place it shows and which exposes the Find Files .. in the File Menu) this will search thru DDBs looking for internal files by file spec and/or by internal file date you can search by comment or size too it will then list them by the parent DDB and when you dbl click on the DDB it opens the and it doesn't start a second copy of 99SE Dennis Saputelli -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PEDA] 99SE Find Files Found
Mike, You got that right, it powerful, and simple at the same time. It will be around for a long time. The current incarnation is mostly a programmers abomination and a companies capitalization of name and brand recognition. For just doing schematics and boards P99 is the pinnacle of the EDA tools. I feel qualified because I use some competitor tools also, but hey I need to earn money as I wasn't born rich so I work. Joe - Original Message - From: edsi [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 07, 2004 9:15 AM Subject: [PEDA] PEDA] 99SE Find Files Found Dennis wrote i just stumbled (after all this time!) on ctrl-F when in the main file list in the RIGHT window (only place it shows and which exposes the Find Files .. in the File Menu) 99SE SP6 is truly an amazing program. I don't think Altium knows how powerful this program is. Sure, it has a few minor quirks, but I am always amazed. After 6 years, I discovered something last week also. I use net classes to define almost all of my routing. You can a select net, or a group of nets and automatically add them to new or existing net class. The option is not available by using the class generator, where I would expect it to be. It only becomes available for use after you make your selections, and the yellow button is turned on below the double arrow in the class generator menu. I stumbled onto this after looking for easier methods to create net classes. Dennis thanks for the tip.I will explore with it Mike Reagan EDSI Frederick ,MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unconnected Ports
Yes Jeff what most of us do is run an ERC(electrical Rules Check), it is evoked under the tools dropdown - Original Message - From: Jeff Condit [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 07, 2004 12:46 PM Subject: [PEDA] Unconnected Ports In Protel 99SE Schematic, a couple ports were positioned a few thousandths of an inch away from a wire and hence made no connection. This made the pins not get included in the netlist. The distance was too small to see in a quick visual check. Is there a way to quickly mark and find unconnected wire ends? Jeff Condit * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
