Re: [PEDA] Flex do's and don'ts ?

2004-10-12 Thread Dennis Saputelli
i am doing my first flex circuit
other than 'talk to my fabricator'
(which i am doing except for language and time zone issues)
is there any such thing as a standard
material callout for thickness?
or a unit of incrementing the requested thickness ?
something comparable to the good old 062 050 031 callouts ?
our requirement is 'pretty thin, but not too thin' :}
(i.e. no particular dimensional requirement)
also i wonder how to call out the copper thickness
i want that 'pretty thick'
it will be made in China, so i guess it will be metric units
i am trying to stay with normal materials and ranges
so we don't ask for more than we need
it will be plated through and needs to take a pretty sharp
bend radius
i sort of remember reading once that trace turns (corners)
should be radiused
is this true?
anyone have a compendium of do's and don'ts ?
the fabricator says they do 2.6 mil traces standard
and up to 7 layers
odd layer counts ok
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Forum Administrator wrote:
At 02:44 PM 10/12/2004, you wrote:
Joe Sapienza wrote:
Good luck

You said it.  The poster may have better luck e-mailing directly to 
Altium.  Screaming in a private forum is not going to get much 
results. It will not even make it to the intended audience.

Hamid

Hamid,
Since you brought it up, I thought you should know that these forums 
enjoy a rather large Altium audience. Altium subscribers include those 
from the lowest ranks to the very top. You won't get an Altium response 
on this forum but you'll surly be heard.

Forum Administrator
Association of Protel EDA Users
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Re: [PEDA] CORE THICKNESSES

2004-10-03 Thread Dennis Saputelli

is there a table of standard core thicknesses somewhere?

i have a 6 layer stackup

top
prepreg
sig
core
gnd
prepreg
pwr
core
sig
prepreg
bott

and am trying to hit 062 overall thickness within +-005

what are all the material thickness possibilities out there?
(well maybe not ALL of them :) )

given 007 prepreg and 021 cores
my vendor tells me that once you add the copper thickness at 1oz
the overall is about 071 thick

sounds like 017 cores would do it, but that also sounds like a wierd number

thanks for any help


Dennis Saputelli


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2851 21st StreetFax: 415-647-3003
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Re: [PEDA] CORE THICKNESSES

2004-10-03 Thread Dennis Saputelli
thanks Harry  Jeff
the guidlines were good
i am not doing impedance control, and they show more thicknesses than i
had imagined - glad i'm not a fab shop!

looks like i can pick one that will be plenty close
and run that by my fab now that i am not just picking numbers out of
the air

Dennis Saputelli



H. Selfridge wrote:
 
 The standard thickness of core material depends on who makes the laminates
 used by your fab.
 
 If your fab can't make the board to your required dimensions, you need to
 call around and see what other fabs can get/do.
 
 An example of available material from one laminate manufacturer can be seen at:
 http://www.chemitalic.dk/content/articles/dfmmatsel.htm
 A table of available laminates can be seen in design guidelines from a fab at:
 http://www.tru-lon.co.uk/pdf/guidelines.pdf
 
 Finished thickness for prepreg and some cores can be different from the raw
 thickness as supplied.  When heated and pressed in the laminating press,
 some reduction in thickness of the individual layers tends to occur.  The
 data sheet from the laminate manufacturer gives the raw and finished
 thicknesses.  Again, the best source of information is from the fab.  If
 you're controlling impedance, the finished thickness data is essential for
 modeling stripline and microstrip characteristics.
 
 At 11:56 AM 10/3/04, you wrote:
 
 is there a table of standard core thicknesses somewhere?
 
 i have a 6 layer stackup
 
 top
  prepreg
 sig
  core
 gnd
  prepreg
 pwr
  core
 sig
  prepreg
 bott
 
 and am trying to hit 062 overall thickness within +-005
 
 what are all the material thickness possibilities out there?
 (well maybe not ALL of them :) )
 
 given 007 prepreg and 021 cores
 my vendor tells me that once you add the copper thickness at 1oz
 the overall is about 071 thick
 
 sounds like 017 cores would do it, but that also sounds like a wierd number
 
 thanks for any help
 
 
 Dennis Saputelli
 
 
 --
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com
 
 
 

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Re: [PEDA] Possible Bug in 99SE?

2004-09-23 Thread Dennis Saputelli
i have NEVER seen anything like that
not even sure how that would be possible given that
there is no cache for the PCB parts

can you describe a little more about the nature of the
changes and differences between old and new parts ?

almost sounds like the image in memory is confused

i bet if you close the file and reopen you will not be able 
to reproduce the problem

Dennis Saputelli



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Re: [PEDA] Electra router

2004-09-14 Thread Dennis Saputelli
here is the link to the article by Mike re Electra tip

http://www.connecteda.com/doc/Autorouting%20Techniques.pdf

it is pretty interesting, exp the strategy re via to via spacing 
rule

Dennis Saputelli


edsi wrote:
 
 Len
 
 I suspect you also typed route and walked away to drink your coffee while the board 
 routed.  Was this after you used the autoplacement tools?  Take a deep breath, put 
 you reading glasses on and read the article I wrote for Electra.   I have no vested 
 interest in this with Electra, (unlike some others on this list).   If you follow 
 the format I outlined, you will learn to use an autorouter.I learned from a 
 fellow named FRANK FRANK.  That is not a typo  that is his both his first and last 
 names. After attending numerous and useless canned demos and  seminars with 
 Cadence,  Frank  opened my eyes on how to use autorouters.Frank  has also 
 endorsed this router.  I would have to say he is one of the foremost experts in 
 autorouting I have ever met.   Please dont type route and walk away from the PC 
 again, your boss might think you can be replaced with software.
 
 It is not a matter of free speech,   it is a matter of saying something that is 
 totally wrong.   Doesnt any one have any integrity anymore?  The router works well.
 
 Mike Reagan
 
 -- Original Message --
 From: Leonard Gabrielson [EMAIL PROTECTED]
 Reply-To: Protel EDA Forum [EMAIL PROTECTED]
 Date:  Mon, 13 Sep 2004 19:55:01 -0700
 
 So much for freedom of speech.
 
 I downloaded the Electra router, and really wanted to give it a fair shake.
 I was very optimistic when I started, but it didn't take long to become
 very, very disappointed.
 
 99SE is far superior.
 
 Len
 
 
 - Original Message -
 From: edsi  [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Monday, September 13, 2004 6:04 PM
 Subject: Re: [PEDA] time to upgrade 99SE? / Electra router
 
 
  Jon
 
  I dont believe for a minute that you know what you are doing.  These are
 some pretty harsh words but dont blast a product (ELECTRA)that failed to
 route only becuase you dont understand how it works. If Electra didnt work
 then Spectra wont work either.   SPECCTRA is a world class router, whose
 performance has not been equaled.  I dont expect you could get this router
 to work either.   The command set is the same for both routers... so
 SPECCTRA sucks too ...right?
 
  Learn to use the damm program before you release your ignorant opinion.
 
  Mike Reagan
 
 
 
 
 
  -- Original Message --
  From: Jon Elson [EMAIL PROTECTED]
  Reply-To: Protel EDA Forum [EMAIL PROTECTED]
  Date:  Mon, 13 Sep 2004 16:59:29 -0500
 
  I finally downloaded the Electra router and tried it on a board
  I had just routed with the P99SE default router.  I thought Protel
  did badly, but the Electra board was a nightmare.  It wasn't
  even able to complete all the nets, it left about 5 undone.
  Protel made a fair jumble of traces all over the place, but Electra
  literally filled the entire area within the keepout border with tracks!
  
  I can't say for sure whether I had all the settings right (actually, I
  haven't
  found anywhere in Electra to set options, etc.) so I'm not sure this
  is a good comparison, yet, but so far I'm not very impressed, to
  say the least.
  
  Since this was discussed a while ago, I thought I would give a report.
  
  Jon
  
  
  
  
 
 
 
 
 
 

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com



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Re: [PEDA] Cannot click pcb parts from DXP

2004-09-13 Thread Dennis Saputelli
thanks i'll look at that

ds


Darren wrote:
 
 Hi Dennis,
 
 Looks like the bit that selects that is in the
 4th line as shown below, this is an ASCII version
 of the file. 1780 is the stack bit checked
 and 1720 is unchecked, you might be able to
 do a change in a text editor, but that would
 depend on what other bits might be set also.
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1720
 1
 1 1 1
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1780
 1
 1 1 1
 
 Not sure what the problem is with the double click
 looks like the component area has a problem, save
 to ASCII might fix that also. Just tried opening
 a ex-dxp file from 2004 and the pad stack enable
 is checked.. :(
 
 Regards,
 Darren Moore
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 
 
  we are working on a board which is a substantial variant of a board
  which was done in DXP (not in P2004) by someone else
 
  my working file was saved back to 99SE which is what we are using
 
  i notice a few anomalies and wonder if there is any comment
 
  some, but not all, components cannot be dbl clicked to edit
 
  later we discovered that dbl clicking somewhere nearby but not
  particularly close to the component made the edit function work
  what is up with that ?
 
  another thing
  it seems that the pads of all components all have the 'enable
  padstack'
  enabled
  and of course that is not one of the properties available as a global
  edit in 99SE
 
  does the save back to 99SE always make 'use padstack' enabled
  because it
  is the norm in DXP?
  i am not sure this is a problem but it was at least a curiosity for me
 
  Dennis Saputelli
 
  --
  __
  _
  Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
  2851 21st StreetFax: 415-647-3003
  San Francisco, CA 94110 www.integratedcontrolsinc.com

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Cannot click pcb parts from DXP

2004-09-13 Thread Dennis Saputelli
when i save as ASCII in 99SE and examine the file
i don't see anything like what you show below re stack
i see records which are one per line
and when i search the file for either 
'DEFAULTS' or '1780'
neither is found

however saving the file as ASCII did appear to correct the component area
problem

so it does not look like the DXP to 99SE save back is exactly
seamless

Dennis Saputelli



Darren wrote:
 
 Hi Dennis,
 
 Looks like the bit that selects that is in the
 4th line as shown below, this is an ASCII version
 of the file. 1780 is the stack bit checked
 and 1720 is unchecked, you might be able to
 do a change in a text editor, but that would
 depend on what other bits might be set also.
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1720
 1
 1 1 1
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1780
 1
 1 1 1
 
 Not sure what the problem is with the double click
 looks like the component area has a problem, save
 to ASCII might fix that also. Just tried opening
 a ex-dxp file from 2004 and the pad stack enable
 is checked.. :(
 
 Regards,
 Darren Moore
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 
 
  we are working on a board which is a substantial variant of a board
  which was done in DXP (not in P2004) by someone else
 
  my working file was saved back to 99SE which is what we are using
 
  i notice a few anomalies and wonder if there is any comment
 
  some, but not all, components cannot be dbl clicked to edit
 
  later we discovered that dbl clicking somewhere nearby but not
  particularly close to the component made the edit function work
  what is up with that ?
 
  another thing
  it seems that the pads of all components all have the 'enable
  padstack'
  enabled
  and of course that is not one of the properties available as a global
  edit in 99SE
 
  does the save back to 99SE always make 'use padstack' enabled
  because it
  is the norm in DXP?
  i am not sure this is a problem but it was at least a curiosity for me
 
  Dennis Saputelli
 
  --
  __
  _
  Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
  2851 21st StreetFax: 415-647-3003
  San Francisco, CA 94110 www.integratedcontrolsinc.com

-- 
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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Cannot click pcb parts from DXP

2004-09-13 Thread Dennis Saputelli
from 99SE assci file 
here is a record of no pad stack followed by one with padstack

|RECORD=Pad|COMPONENT=0|SELECTION=FALSE|LAYER=MULTILAYER|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|NAME=5|X=6760mil|Y=5980mil|XSIZE=62mil|YSIZE=62mil|SHAPE=ROUND|HOLESIZE=32mil|ROTATION=180.000|PLATED=TRUE|DAISYCHAIN=Load|CCSV=0|CPLV=0|CCWV=1|CENV=1|CAGV=1|CPEV=1|CSEV=1|CPCV=1|CPRV=1|CCW=10mil|CEN=4|CAG=10mil|CPE=0mil|CSE=4mil|CPC=20mil|CPR=20mil

|RECORD=Pad|COMPONENT=0|SELECTION=FALSE|LAYER=MULTILAYER|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|NAME=6|X=6860mil|Y=5980mil|TOPXSIZE=62mil|MIDXSIZE=61mil|BOTXSIZE=62mil|YSIZE=62mil|SHAPE=ROUND|HOLESIZE=32mil|ROTATION=180.000|PLATED=TRUE|DAISYCHAIN=Load|CCSV=0|CPLV=0|CCWV=1|CENV=1|CAGV=1|CPEV=1|CSEV=1|CPCV=1|CPRV=1|CCW=10mil|CEN=4|CAG=10mil|CPE=0mil|CSE=4mil|CPC=20mil|CPR=20mil


Dennis Saputelli

Darren wrote:
 
 Hi Dennis,
 
 Looks like the bit that selects that is in the
 4th line as shown below, this is an ASCII version
 of the file. 1780 is the stack bit checked
 and 1720 is unchecked, you might be able to
 do a change in a text editor, but that would
 depend on what other bits might be set also.
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1720
 1
 1 1 1
 
 ENDCOMP
 DEFAULTS
 0 0
 900 1780
 1
 1 1 1
 
 Not sure what the problem is with the double click
 looks like the component area has a problem, save
 to ASCII might fix that also. Just tried opening
 a ex-dxp file from 2004 and the pad stack enable
 is checked.. :(
 
 Regards,
 Darren Moore
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 
 
  we are working on a board which is a substantial variant of a board
  which was done in DXP (not in P2004) by someone else
 
  my working file was saved back to 99SE which is what we are using
 
  i notice a few anomalies and wonder if there is any comment
 
  some, but not all, components cannot be dbl clicked to edit
 
  later we discovered that dbl clicking somewhere nearby but not
  particularly close to the component made the edit function work
  what is up with that ?
 
  another thing
  it seems that the pads of all components all have the 'enable
  padstack'
  enabled
  and of course that is not one of the properties available as a global
  edit in 99SE
 
  does the save back to 99SE always make 'use padstack' enabled
  because it
  is the norm in DXP?
  i am not sure this is a problem but it was at least a curiosity for me
 
  Dennis Saputelli
 
  --
  __
  _
  Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
  2851 21st StreetFax: 415-647-3003
  San Francisco, CA 94110 www.integratedcontrolsinc.com

-- 
___
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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Cannot click pcb parts from DXP

2004-09-11 Thread Dennis Saputelli

we are working on a board which is a substantial variant of a board
which was done in DXP (not in P2004) by someone else 

my working file was saved back to 99SE which is what we are using

i notice a few anomalies and wonder if there is any comment

some, but not all, components cannot be dbl clicked to edit

later we discovered that dbl clicking somewhere nearby but not 
particularly close to the component made the edit function work
what is up with that ?

another thing
it seems that the pads of all components all have the 'enable padstack'
enabled
and of course that is not one of the properties available as a global 
edit in 99SE

does the save back to 99SE always make 'use padstack' enabled because it 
is the norm in DXP?
i am not sure this is a problem but it was at least a curiosity for me

Dennis Saputelli

-- 
___
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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] 99SE Find Files Found

2004-09-07 Thread Dennis Saputelli

i just stumbled (after all this time!) on
ctrl-F when in the main file list in the RIGHT window
(only place it shows and which exposes the Find Files .. in the File Menu)

this will search thru DDBs looking for internal files by file spec 
and/or by internal file date
you can search by comment or size too

it will then list them by the parent DDB and when you dbl click on the
DDB it opens the and it doesn't start a second copy of 99SE

Dennis Saputelli

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com



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Re: [PEDA] Unconnected Ports

2004-09-07 Thread Dennis Saputelli
good question
not that i know of, but would be interested if it is possible

the ERC does show some of these things but apparently not
ports

for this reason i have made a habit of leaving the grid always on in SCH

for the occasions when that is inappropriate did you know that holding the
ctrl key will suspend the grid while say wiggling bits of things like text
about ?
(an interesting buglet here:
the coord display shows as if grid is on but the actual action is correct)

also i programmed ctrl-g to toggle the grid on and off this makes it
bit easier to stay on grid compared to having to paw through the menus

also the watch for the hot spot markers while drawing, this helps
monitor connectivity

ds


Jeff Condit wrote:
 
 In Protel 99SE Schematic, a couple ports were positioned a few thousandths of an 
 inch away from a wire and hence made no connection.  This made the pins not get 
 included in the netlist.  The distance was too small to see in a quick visual check. 
  Is there a way to quickly mark and find unconnected wire ends?
 
 Jeff Condit

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Re: [PEDA] Unconnected Ports

2004-09-07 Thread Dennis Saputelli
JOE
the ERC will not flag PORTS (AFAIK)
power ports and other stuff yes

it is interesting that it really doesn't want to let you place a port
unless it is going to be connected

you can trick it or move it later but try to just place one in the air,
it will erase it automatically if it was not at least initially connected

Dennis Saputelli


Joe Sapienza wrote:
 
 Yes Jeff what most of us do is run an ERC(electrical Rules Check), it is
 evoked under the tools dropdown
 
 - Original Message -
 From: Jeff Condit [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Tuesday, September 07, 2004 12:46 PM
 Subject: [PEDA] Unconnected Ports
 
 In Protel 99SE Schematic, a couple ports were positioned a few thousandths
 of an inch away from a wire and hence made no connection.  This made the
 pins not get included in the netlist.  The distance was too small to see in
 a quick visual check.  Is there a way to quickly mark and find unconnected
 wire ends?
 
 Jeff Condit
 

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Re: [PEDA] PEDA] 99SE Find Files Found

2004-09-07 Thread Dennis Saputelli
this file lister is just what i have been asking for ages
can't believe i never saw it 

it will list all the internal file details across multiple DDBs

it somewhat ameliorates the DDB file date issue since you can
easily see the internal file dates without opening all the DDBs in question

Dennis Saputelli

edsi wrote:
 
 Dennis wrote
 
  i just stumbled (after all this time!) on
  ctrl-F when in the main file list in the RIGHT window
  (only place it shows and which exposes the Find Files .. in the File Menu)
 
 
 99SE SP6 is truly an amazing program.  I don't think  Altium knows how powerful this 
 program is.   Sure, it has a few minor quirks, but I am always amazed.   After 6 
 years,  I discovered something last week also.   I use net classes to define almost 
 all of my routing.  You can a select net, or a group of nets and automatically add 
 them to new or existing net class.  The option is not available by using the class 
 generator, where I would expect it to be.  It only becomes available for use after 
 you make your selections, and the yellow button is turned  on below the double arrow 
 in the class generator menu.   I stumbled onto this after looking for  easier 
 methods to create net classes.
 
 Dennis thanks for the tip.I will explore with it
 
 Mike Reagan
 EDSI
 Frederick ,MD
 

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Re: [PEDA] tests for Pb in solder

2004-08-13 Thread Dennis Saputelli

very sobering and interesting article in 
Printed Circuit Design and Manufacturing on this topic:

the title is 
Why Lead-free Feels Like the End

http://pcdandm.com/pcdmag/mag/0408/0408roi.pdf

Dennis Saputelli


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Re: [PEDA] Orcad schem part field for TOPSIDE or BOTTSIDE

2004-08-10 Thread Dennis Saputelli
seems like this would be possibly a nice feature to optionally control
from the schematic and be fully automatic
if you didn't like the result you could 
still muck about with the parts selectively

Orcad capture also has what i think is a new feature to v. 10:
a big spreadsheet type panel with all the objects across all the 
sheets which can be sorted by their columns 
and which can be used to globally
edit things reasonably simply

Dennis Saputelli


Ian Wilson wrote:
 
 On 03:07 AM 10/08/2004, Dennis Saputelli said:
 
 Orcad Capture has a schem part field for TOPSIDE or BOTTSIDE
 
 is there a way in 99SE or P2004 to get the netlist to
 dump the part on the indicated side of the board ?
 
 No, not automatically.
 
 You could use a part field (99SE) or a parameter (DXP/P2004) to indicate
 what side and then select and change globally - you would need a method to
 select components in the PCB based on what is selected in the Sch - can
 this be done in P99SE?  (P2004 has a command to select PCB components based
 on what is selected in Sch, it works for components selected on multiple
 sheets. I can't recall if P99SE has this.)
 
 A script could do the layer flip in P2004 (iterate over all components and
 flip any that are on the wrong layer compared to the parameter/part
 field).  Not sure if a macro could do it in P99SE, it may be able to but
 macro functionality is quite limited.  A server could do it in
 P99SE.  There are some tricks as you would need to deal with of course as
 the PCB components do not carry the part fields/parameters so you need to
 go back and compare with the Sch or the netlist.
 
 Ian
 

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Re: [PEDA] Orcad schem part field for TOPSIDE or BOTTSIDE

2004-08-10 Thread Dennis Saputelli
In the case of this new orcad feature you specifically do it
'outside' of the graphical sch
you point to sheets and it gathers a properties page
kind of like a batch process

ds


Ian Wilson wrote:
 
 On 10:31 AM 11/08/2004, Dennis Saputelli said:
 seems like this would be possibly a nice feature to optionally control
 from the schematic and be fully automatic
 if you didn't like the result you could
 still muck about with the parts selectively
 
 Yep.  I agree.  Users have been suggesting a number of things (on the DXP
 forum) that increase the ability to control layout from sch.  Things like
 setting layers and being able to create classes (nets, components etc) in
 the sch.  Maybe some of these ideas will appear at some stage.
 
 Orcad capture also has what i think is a new feature to v. 10:
 a big spreadsheet type panel with all the objects across all the
 sheets which can be sorted by their columns
 and which can be used to globally
 edit things reasonably simply
 
 Sort of like DXP/P2004's List panel is it?  P99SE has this but you have to
 export-change-import and this is a somewhat fiddly process.
 
 One of my dislikes about P2004 is that the List panel is always active
 (even if not visible).  The List panel is great when necessary but filling
 it and emptying it *might* be a cause of delays when doing queries that
 affect lots of objects - there are delays but us users are not privy to all
 the causes, I hypothesize that the List panel is one cause.  I say might as
 there is no way of confirming whether this is the case, but it is a
 possibility.
 
 However there are times when the List panel is very useful. You can sort by
 clicking on column headers.  You can edit a bunch of objects at the same
 time. You can show child objects of group objects (polygons, components
 etc).  Managing the columns that are shown could be better I think.  The
 List, like the Inspector, by default only shows columns that are common to
 all the objects returned by the current filter.  So when no filter is
 active it shows everything and so you don't have many useful columns - you
 can turn on more columns manually.
 
 The main issue I have with P2004 implementation of the List panel
 (spreadsheet view) is that keeping it up-to-date is possibly a cause of
 these pregnant pauses that one gets while running some queries/filters. I
 would like to be able to turn off the List panel so it is not having to be
 continually kept synched with the current filters.
 
 Ian

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Re: [PEDA] Orcad schem part field for TOPSIDE or BOTTSIDE

2004-08-09 Thread Dennis Saputelli

Orcad Capture has a schem part field for TOPSIDE or BOTTSIDE

is there a way in 99SE or P2004 to get the netlist to
dump the part on the indicated side of the board ?


Dennis Saputelli


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Re: [PEDA] P99SE installation

2004-08-05 Thread Dennis Saputelli
have you asked protel?
they should know specfically

i suspect it is the order of installation of the various
packages

and of course lots of rebooting between installations
i am always amazed at how much that helps resolve 
strange installation issues

Dennis Saputelli


Alfonso Baz wrote:
 
 I'm curious if anybody else has noticed the following when installing P99SE
 SP6 on either WIN2K or WINXP.
 
 
 
 Recently I upgraded my PC. I noticed after a clean OS install followed by
 installation of my usual software packages, windows Start-Help and
 Support didn't work. Also right-clicking My Computer on the desktop and
 selecting Manage failed to respond.
 
 Thanks to XP's system restore, I found the offending software installation.
 P99SE
 
 
 
 I'm looking into it at the moment already spent a few hours here and there,
 thought someone might be able to help me out
 
 
 
 Thanks
 
 Alfonso
 
 
 
 

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Re: [PEDA] changing power symbols

2004-08-02 Thread Dennis Saputelli
ok so now we have a challenge! (albeit a meaningless 
and stupid challenge which is always the best kind)

those pesky power symbols must coded in there somewhere!

time to start sniffing around the binary files

Dennis Saputelli

Leo Potjewijd wrote:
 
 At 31-7-2004 13:34, Rolf Molitor wrote:
 You can edit the power symbols like this:
 Get the System Menu (down arrow) and select Customize.
 Right click the Power objects and select Edit. There you see all your
 actual power objects.
 You can add new power objects here or change the existing ones with right
 click and New or Properties.
 When you select Properties you will see what bitmap file this power object
 uses. Just edit the bitmap to change the view of the power object.
 
 Rolf,
 I probably am doing something wrong, but all I can edit when I follow you
 description is the button in the toolbar and not the actual power object
 itself as it appears on the schematic
 
 Leo Potjewijd
 hardware designer
 Integrated Engineering B.V.
 
 [EMAIL PROTECTED]
 +31 20 4620700
 

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Re: [PEDA] changing power symbols

2004-08-02 Thread Dennis Saputelli
according to Leo they don't meet his drawing standards requirements
in the Netherlands

Dennis Saputelli


John A. Ross [RSDTV] wrote:
 
 Dennis
 
 Other than for the pure heck of it (as you say, sometimes a valid reason :-) ), what 
 other graphic
 symbols are actually needed for a power port ?
 
 We have bar/circle/arrow/earth
 
 Leo, what additional symbols were you after in your original post ?
 
 John
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
  Sent: Monday, August 02, 2004 4:27 PM
  To: Protel EDA Forum
  Subject: Re: [PEDA] changing power symbols
 
  ok so now we have a challenge! (albeit a meaningless and
  stupid challenge which is always the best kind)
 
  those pesky power symbols must coded in there somewhere!
 
  time to start sniffing around the binary files
 
  Dennis Saputelli
 
  Leo Potjewijd wrote:
  
   At 31-7-2004 13:34, Rolf Molitor wrote:
   You can edit the power symbols like this:
   Get the System Menu (down arrow) and select Customize.
   Right click the Power objects and select Edit. There
  you see all
   your actual power objects.
   You can add new power objects here or change the existing
  ones with
   right click and New or Properties.
   When you select Properties you will see what bitmap file
  this power
   object uses. Just edit the bitmap to change the view of
  the power object.
  
   Rolf,
   I probably am doing something wrong, but all I can edit
  when I follow
   you description is the button in the toolbar and not the
  actual power
   object itself as it appears on the schematic
  
   Leo Potjewijd
   hardware designer
   Integrated Engineering B.V.
  
   [EMAIL PROTECTED]
   +31 20 4620700
  
 
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Re: [PEDA] changing power symbols

2004-07-30 Thread Dennis Saputelli
you cant make your own power symbols

but if you make a part with a pin (it can be very short)
you should get a hot spot
of course these parts would show in your BOM
but this is where 'include blank part value' checkbox 
comes in handy, should be acceptable

what do y'all use across the pond anyway ?


Dennis Saputelli


Leo Potjewijd wrote:
 
 Hi,
 at the risk of asking an old question:
 Has anyone found a way to change the shape of the built-in power symbols of
 P99SE? We use different symbols here in Europe
 I know I can build my own (I have a wide collection of them) but the lack
 of an electrical hotspot on these is (finally) getting to my nerves
 
 Leo Potjewijd
 hardware designer
 Integrated Engineering B.V.
 
 [EMAIL PROTECTED]
 +31 20 4620700
 
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Re: [PEDA] 99SE SP6 updating footprints

2004-07-29 Thread Dennis Saputelli
works for me too
i have found that occasionally i need to point to
another lib and back to the first one to refresh the list

ds


Wojciech Oborski wrote:
 
 I may confirm the behaviour that Leo described -
 - after adding/removing a component to/from a library, going back to PCB Editor,
 clicking on a library name in Explorer Window (Browse PCB tab) -
 - the Components list is updated.
 It means - it works for me.
 
 Regards,
 Wojciech Oborski
 
 Leo Potjewijd wrote:
 
 snip
  John,

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Re: [PEDA] 99SE SP6 updating footprints

2004-07-28 Thread Dennis Saputelli
there is no cache for PCB footprints
(as there is for sch)

when i did just what you described in your 1st paragraph
only the component i was working on changed but
the footprint field names changed in all the instances

BUT THAT WAS LAST night on a different machine

this morning i cannot reproduce the behavoir on a different box
i even tried variations of mistakes i might have made 
like 'all free' vs 'free prims'

go figure

Igor's comment about going back to the leb editor and hitting
the update might have worked once the footprint strings were stuffed
in but now i can test it

Dennis Saputelli


John A. Ross [Design] wrote:
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
  Sent: 28 July 2004 02:24
  To: Protel EDA Forum
  Subject: Re: [PEDA] 99SE SP6 updating footprints
 
  i'm sure this has been discussed (?)
  but i just noticed the following in 99SE PCB
 
  if you have several or more parts of the same footprint on a
  board and you type in a new and valid footprint name and do
  the global thing: copy footprint, footprint=same
 
  the one you are editing changes to the new footprint and all
  the others acquire the NEW FOOTPRINT NAME from the global
  operation but the footpints don't change to the new one
 
 Dennis
 
 Not quite sure what you mean here.
 
 I tried what I think you were describing quickly on a board here. I
 picked a 0603 part, changed the value in the footprint field to 0805,
 clicked global (footprint already checked) and set the combo box to
 footprint=same, clicked OK and all 202 items were changed OK.
 
 If I change the footprint field to a value which does not represent a
 valid footprint name in the library, then I see a global change in the
 footprint name according to the selection and no footprint change is
 applied, but I get a warning for every update instance that fails
 (footprint not in library), you don't mention a warning, and you state
 you used a valid footprint name, so I guess this is not the same as you
 are seeing.
 
 But I have seen some very strange behaviour with differences with the
 loaded (cached) library and the actual library where you have to
 drop/reload the library to update it. Not sure 'where' the actual pcb
 being edited 'looks' for the valid footprint but I would guess it would
 be the cached one so if the new valid footprint was added after the
 library was added/cached to the PCB editor then something like this
 could be possible I guess
 
 Do not know if this helps you any.
 
 John

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Re: [PEDA] 99SE SP6 updating footprints

2004-07-28 Thread Dennis Saputelli
each PCB part has it's own separate and complete 
instance in the PCB file
(this is how you are able to unlock prims and move something and
not change the others)

the push process from the lib editor simply matches the footprint
name changes them to the new version

Dennis Saputelli


John A. Ross [RSDTV] wrote:
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 28, 2004 6:19 PM
  To: Protel EDA Forum
  Subject: Re: [PEDA] 99SE SP6 updating footprints
 
  there is no cache for PCB footprints
  (as there is for sch)
 
 Dennis
 
 There must be some type of cache for the PCB library, or cache might not be the 
 correct term.
 
 If some sort of cache is not used then footprints would be updated every time the 
 PCB was opened
 from the pre-loaded libraries or the library was changed, it would not require a 
 'push' process like
 update PCB to do it.
 
 If say
 
 PCB editor is open with MYLIB library loaded,
 I open MYLIB for editing,
 I then add a new footprint to MYLIB, save and close it,
 If I browse the library within the PCB editor the new footprint is not yet available
 A push process of update PCB still does not make the footprint available.
 If I remove MYLIB and then add it back in the new footprint is now available for use.
 
 Always found it to be this way ;-)
 
 John
 
  when i did just what you described in your 1st paragraph only
  the component i was working on changed but the footprint
  field names changed in all the instances
 
  BUT THAT WAS LAST night on a different machine
 
  this morning i cannot reproduce the behavoir on a different
  box i even tried variations of mistakes i might have made
  like 'all free' vs 'free prims'
 
 
  go figure
 
  Igor's comment about going back to the leb editor and hitting
  the update might have worked once the footprint strings were
  stuffed in but now i can test it
 
  Dennis Saputelli
 
 
  John A. Ross [Design] wrote:
  
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
Sent: 28 July 2004 02:24
To: Protel EDA Forum
Subject: Re: [PEDA] 99SE SP6 updating footprints
   
i'm sure this has been discussed (?) but i just noticed the
following in 99SE PCB
   
if you have several or more parts of the same footprint
  on a board
and you type in a new and valid footprint name and do the global
thing: copy footprint, footprint=same
   
the one you are editing changes to the new footprint and all the
others acquire the NEW FOOTPRINT NAME from the global
  operation but
the footpints don't change to the new one
  
   Dennis
  
   Not quite sure what you mean here.
  
   I tried what I think you were describing quickly on a board here. I
   picked a 0603 part, changed the value in the footprint
  field to 0805,
   clicked global (footprint already checked) and set the combo box to
   footprint=same, clicked OK and all 202 items were changed OK.
  
   If I change the footprint field to a value which does not
  represent a
   valid footprint name in the library, then I see a global
  change in the
   footprint name according to the selection and no footprint
  change is
   applied, but I get a warning for every update instance that fails
   (footprint not in library), you don't mention a warning,
  and you state
   you used a valid footprint name, so I guess this is not the same as
   you are seeing.
  
   But I have seen some very strange behaviour with
  differences with the
   loaded (cached) library and the actual library where you have to
   drop/reload the library to update it. Not sure 'where' the
  actual pcb
   being edited 'looks' for the valid footprint but I would guess it
   would be the cached one so if the new valid footprint was
  added after
   the library was added/cached to the PCB editor then something like
   this could be possible I guess
  
   Do not know if this helps you any.
  
   John
 
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  __
  _
  Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
  2851 21st StreetFax: 415-647-3003
  San Francisco, CA 94110 www.integratedcontrolsinc.com
 
 
 
 

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Re: [PEDA] 99SE SP6 updating footprints

2004-07-27 Thread Dennis Saputelli

i'm sure this has been discussed (?)
but i just noticed the following in 99SE PCB

if you have several or more parts of the same footprint on a board
and you type in a new and valid footprint name
and do the global thing: copy footprint, footprint=same

the one you are editing changes to the new footprint and all
the others acquire the NEW FOOTPRINT NAME from the global operation 
but the footpints don't change to the new one

is there some trick here to force them all ?

they are place and i don't want to delete and reload nets
to get them

Dennis Saputelli


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Re: [PEDA] stopping second instance of 99SE

2004-07-26 Thread Dennis Saputelli
i couldn't find the thread you mentioned either

i wrote protel support about this
we will see if they answer, so far not yet

what is driving this in part is that we have a zillion projects
all over the place in fairly complex directory structures

we often open mnay DDBs for either design reference or to swipe
details or parts

if you use protel to drill around to open files, then aside
from a lot of worthless time spent, it leaves protel
pointing to the wrong folder for the next operation

we have a couple of good file managers that will pop us to the
right spot with minimal fuss 
so the working method here is to locate the file then apply it to
the app, works great for autocad and PDFs and most other progs

Dennis Saputelli


[EMAIL PROTECTED] wrote:
 
 Steve,
 
 I think you may have misunderstood me. IFF my memory serves me
 correctly, the discussion was about disabling only the second execution,
 not dis-associating the .ddb extension from Protel or otherwise
 compromising the natural windows double-click execution of a program
 based on association(s).
 
 Though admittedly, is there isn't another method, then what you're
 suggesting is probably the only thing that Dennis can do to stop the
 second (or third...) instance from occurring when a .ddb file is
 double-clicked...
 
 aj
 
 -Original Message-
 From: Steve Wiseman [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 6:49 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 23/07/2004 16:51:09, [EMAIL PROTECTED] wrote:
 
 I think I remember someone once-upon-a-time (Like Ian
 maybe?) saying
 that multiple instances was a defeatable within p99, either thru
 the ini
 files or perhaps a registry setting..
 
 It's easy enough to just  stop .ddb , .sch, .prj, .pcb and whatever else
 you're likely to double click on being associated with Protel.
 Fire up regedt32 (from task manager, if you can't find it elsewhere),
 then go to HKEY_LOCAL_MACHINE, SOFTWARE, Classes, and delete (click on,
 then hit 'DEL') .ddb and all the others you fancy killing off. That'll
 stop them launching Protel when you double-click, but Protel will still
 be entirely happy to open them. job done, without all this messing about
 with application launcher, counting copies, and the like. The icons may
 no longer be as pretty in file manager. Tough.
 
 Steve

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] stopping second instance of 99SE

2004-07-26 Thread Dennis Saputelli
colby just wrote back from protel and said
no, there is no fix for this

Dennis Saputelli


[EMAIL PROTECTED] wrote:
 
 Steve,
 
 I think you may have misunderstood me. IFF my memory serves me
 correctly, the discussion was about disabling only the second execution,
 not dis-associating the .ddb extension from Protel or otherwise
 compromising the natural windows double-click execution of a program
 based on association(s).
 
 Though admittedly, is there isn't another method, then what you're
 suggesting is probably the only thing that Dennis can do to stop the
 second (or third...) instance from occurring when a .ddb file is
 double-clicked...
 
 aj
 
 -Original Message-
 From: Steve Wiseman [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 6:49 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 23/07/2004 16:51:09, [EMAIL PROTECTED] wrote:
 
 I think I remember someone once-upon-a-time (Like Ian
 maybe?) saying
 that multiple instances was a defeatable within p99, either thru
 the ini
 files or perhaps a registry setting..
 
 It's easy enough to just  stop .ddb , .sch, .prj, .pcb and whatever else
 you're likely to double click on being associated with Protel.
 Fire up regedt32 (from task manager, if you can't find it elsewhere),
 then go to HKEY_LOCAL_MACHINE, SOFTWARE, Classes, and delete (click on,
 then hit 'DEL') .ddb and all the others you fancy killing off. That'll
 stop them launching Protel when you double-click, but Protel will still
 be entirely happy to open them. job done, without all this messing about
 with application launcher, counting copies, and the like. The icons may
 no longer be as pretty in file manager. Tough.
 
 Steve

-- 
___
Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107 
2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] stopping second instance of 99SE

2004-07-26 Thread Dennis Saputelli
yes i know (drag)
but i fumble (or forget) a lot!

also!
2 copies is BAD
at least for us
the libraries loaded become very strange

Dennis Saputelli


Darcy Davis wrote:
 
 Hey Dennis,
 
 I can certainly understand your motivation here. We have a similar situation
 here, although I sometimes like being able to start more than one instance
 of 99SE as it allows me to reference one design on one monitor, and another
 on the other monitor.
 
 Forgive me if you were already aware of this, but instead of double-clicking
 the .ddb file, you can drag and drop it right into whichever instance of
 Protel you're working out of. Works great so long as you can override your
 instinct to double click.
 
 Darcy Davis
 Design Engineer,
 Dynastream Innovations, Inc.
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: July 26, 2004 11:15 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 i couldn't find the thread you mentioned either
 
 i wrote protel support about this
 we will see if they answer, so far not yet
 
 what is driving this in part is that we have a zillion projects
 all over the place in fairly complex directory structures
 
 we often open mnay DDBs for either design reference or to swipe
 details or parts
 
 if you use protel to drill around to open files, then aside
 from a lot of worthless time spent, it leaves protel
 pointing to the wrong folder for the next operation
 
 we have a couple of good file managers that will pop us to the
 right spot with minimal fuss
 so the working method here is to locate the file then apply it to
 the app, works great for autocad and PDFs and most other progs
 
 Dennis Saputelli
 
 [EMAIL PROTECTED] wrote:
 
  Steve,
 
  I think you may have misunderstood me. IFF my memory serves me
  correctly, the discussion was about disabling only the second execution,
  not dis-associating the .ddb extension from Protel or otherwise
  compromising the natural windows double-click execution of a program
  based on association(s).
 
  Though admittedly, is there isn't another method, then what you're
  suggesting is probably the only thing that Dennis can do to stop the
  second (or third...) instance from occurring when a .ddb file is
  double-clicked...
 
  aj
 
  -Original Message-
  From: Steve Wiseman [mailto:[EMAIL PROTECTED]
  Sent: Friday, July 23, 2004 6:49 PM
  To: Protel EDA Forum
  Subject: Re: [PEDA] stopping second instance of 99SE
 
  23/07/2004 16:51:09, [EMAIL PROTECTED] wrote:
 
  I think I remember someone once-upon-a-time (Like Ian
  maybe?) saying
  that multiple instances was a defeatable within p99, either thru
  the ini
  files or perhaps a registry setting..
 
  It's easy enough to just  stop .ddb , .sch, .prj, .pcb and whatever else
  you're likely to double click on being associated with Protel.
  Fire up regedt32 (from task manager, if you can't find it elsewhere),
  then go to HKEY_LOCAL_MACHINE, SOFTWARE, Classes, and delete (click on,
  then hit 'DEL') .ddb and all the others you fancy killing off. That'll
  stop them launching Protel when you double-click, but Protel will still
  be entirely happy to open them. job done, without all this messing about
  with application launcher, counting copies, and the like. The icons may
  no longer be as pretty in file manager. Tough.
 
  Steve
 
 --
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com

-- 
___
Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107 
2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Adobe Illustrator

2004-07-23 Thread Dennis Saputelli
Autocad

you can use all the true type fonts and put the borders and junk
exactly where it is in the design
when the design changes the graphics move with the holes

buts it's a little hard to get the films made right
since most people in that business are mac shops
san jose blue
seems to know what buttons to push but they won't tell me

Dennis Saputelli


RogerHead wrote:
 
 I am considering AI for designing instrument front panels. What do other
 people use? Our publications department people love it, but they're using
 it every day. I'll use it a few times a year. But I want to get away from
 the blocky, 'designed by an engineer' appearance - you know, front panel
 artwork laid out in Protel.
 
 Roger
 

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San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] stopping second instance of 99SE

2004-07-23 Thread Dennis Saputelli
thanks but i don't see how this would do what is wished

i see an option for 'allow only singe copy' 
but that is for the total commander program itself

i messed around for a bit but 2 copies of 99SE
pop up just as always

Dennis Saputelli


Michael Wieser wrote:
 
 Dennis
 
 http://www.ghisler.com
 
 Total Commander, looks like the old Norton Commander,
 
 --
 Michael Wieser ([EMAIL PROTECTED])
 Elektronik und Leiterplattenlayout
 H tzing 6
 A-4906 Eberschwang
 Austria
 Tel: (+43) 7753 3320
 Fax: (+43) 7753 3320 14
 Mobil: (+43) 650 826 59 27
 
 --
 
  BTW
  and on a vaguely related topic
  has anyone tried ExplorerPlus ?
  http://www.novatix.com/
  as i am always in search of a file manager to replace
  the hated (at least by me) Windows Explorer
  i have found this prog and am so far impressed enough that i
  actually shelled out the big bucks ($40) after the free trial run
 
  Dennis Saputelli

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] stopping second instance of 99SE

2004-07-22 Thread Dennis Saputelli
great ! thanks

i will try and report tomorrow

and yes they should have taken care of this for us

Dennis Saputelli


Harry Lemmens wrote:
 
 Supposedly, this app will allow you to control this aspect of windows. I have
 not tried it myself. http://www.softaward.com/732.html
 
 Actually, it should have been written into the application itself (That is, to
 detect, and dis-allow a second instance of itself to be launched!) Done
 correctly, it would have opened the DDB in the already active session.
 
 Cheers
 Harry
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 11:11 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 is there any utility out there that will stop a second instance of
 a program from running when you double click a data file with
 a file associated which would start that program ?
 
 sure would love that, seems like it would be feasible from the
 small amount i know about this stuff
 
 this desire is due to the all too frequent mishap of double
 clicking a DDB instead of or during dragging it to the title bar
 
 after 2 copies are running i have found it a MUST to quit
 them both and restart 99SE, else something goes screwy with the
 loaded libraries
 
 i'm sure i posted this some time ago but thought i would try
 again
 
 Dennis Saputelli
 
 --
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com

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2851 21st StreetFax: 415-647-3003
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Re: [PEDA] stopping second instance of 99SE

2004-07-22 Thread Dennis Saputelli
oh well, thanks anyway Harry

but unless i missed something in my exhaustive :} 3 minute trial
of CONTROL LAUNCHER here is what i see:

the launcher they provide will not start a second copy of the
launched program if the default setting of 'one copy only'
is set and you use their program launch button

but if you dbl click on a DDB in 'explorer' a second copy is 
started up as usual

i would think that it would be possible for a program to
intercept the file association program 'launching' process and 
prevent that but as for now the search goes on
(maybe i am the only one who wants this)

BTW
and on a vaguely related topic
has anyone tried ExplorerPlus ? 
http://www.novatix.com/
as i am always in search of a file manager to replace 
the hated (at least by me) Windows Explorer
i have found this prog and am so far impressed enough that i 
actually shelled out the big bucks ($40) after the free trial run

Dennis Saputelli


Harry Lemmens wrote:
 
 Supposedly, this app will allow you to control this aspect of windows. I have
 not tried it myself. http://www.softaward.com/732.html
 
 Actually, it should have been written into the application itself (That is, to
 detect, and dis-allow a second instance of itself to be launched!) Done
 correctly, it would have opened the DDB in the already active session.
 
 Cheers
 Harry
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 11:11 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 is there any utility out there that will stop a second instance of
 a program from running when you double click a data file with
 a file associated which would start that program ?
 
 sure would love that, seems like it would be feasible from the
 small amount i know about this stuff
 
 this desire is due to the all too frequent mishap of double
 clicking a DDB instead of or during dragging it to the title bar
 
 after 2 copies are running i have found it a MUST to quit
 them both and restart 99SE, else something goes screwy with the
 loaded libraries
 
 i'm sure i posted this some time ago but thought i would try
 again
 
 Dennis Saputelli
 
 --

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Shortcuts in 99SE ?

2004-07-21 Thread Dennis Saputelli

in the 99SE DDB system (not the windows file system) it is not
possible to add a shortcut (or link) to an external file, is it ?
would a be nice feature

Dennis Saputelli


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Re: [PEDA] Shortcuts in 99SE ?

2004-07-21 Thread Dennis Saputelli

John,
we are talking about shortcuts or 'links' not importing the
file itself into the DDB, so i don't see how the wrapper is an issue

Terry,

i can't believe i never noticed that after all these years!
works great for me, PDFs too

but
is see the following issues which i find puzzling:

i started a new MSACCESS DDB design
i dragged in a small schematic and a small board so it would
be something a bit like a real design
both files were very small, 10K + 900K

i then made a LINK to a JPG
the file size in the DDB shows 3M
but the JPG is only 68K
the ICON in the DDB shows the shortcut arrow thingy

then i linked to a PDF
the PDF external file is about 60K and the DDB link file is
about 6K which seems about right

so what is up with the JPG case?

BTW, the PDF pointer works fine, as does the
JPG each launcing their own associated apps

also
can you expose the properties
of the LINK ?
i want to see the path that the link contains
but it is blank in the right click
properties dialog


Dennis Saputelli


Terry Creer wrote:
 
 Hi Dennis,
 
 See page 30 of the P99SE Handbook.
 
 Just right click in a DDB window and choose 'Link' from the menu (the menu
 that contains New, Import, Import Folder, Import Project, Link, View).
 
 Cheers,
 
 TC
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, 21 July 2004 10:31 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Shortcuts in 99SE ?
 
 in the 99SE DDB system (not the windows file system) it is not
 possible to add a shortcut (or link) to an external file, is it ?
 would a be nice feature
 
 Dennis Saputelli
 
 --
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com

-- 
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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] Shortcuts in 99SE ?

2004-07-21 Thread Dennis Saputelli
this is getting embarassing
i thought i knew it all in 99SE
but you can enter a description in the properties
box and it persists and is listed in the file list
never noticed that either
could be very handy

still want to know how to get the path of a linked file
after the fact of linking though

i played with a few LINKs
Jpegs and Gifs appear to be imported and and thus 
the explosion in size
i suspect they are brought in as bitmaps

PDF seems to make a true link
the acrobat title bar says 'embedded' document

DOC file seems to import the whole file at a slight
increase in size so i wondered if these LINK things
are true shortcuts

WAIT, they are true links! even though the JPG file seems
to be imported, changes to the external file are 
reflected in the DDB

i closed the DDB, changed the external JPG file
and reopened the DDB and the change was shown

then i repeated above except with the DDB open 
and it still showed the change when the JPG was reopened

so this is pretty cool
now if it only showed the path, or did i already say that ? :}}

Dennis Saputelli


Dennis Saputelli wrote:
 
 John,
 we are talking about shortcuts or 'links' not importing the
 file itself into the DDB, so i don't see how the wrapper is an issue
 
 Terry,
 
 i can't believe i never noticed that after all these years!
 works great for me, PDFs too
 
 but
 is see the following issues which i find puzzling:
 
 i started a new MSACCESS DDB design
 i dragged in a small schematic and a small board so it would
 be something a bit like a real design
 both files were very small, 10K + 900K
 
 i then made a LINK to a JPG
 the file size in the DDB shows 3M
 but the JPG is only 68K
 the ICON in the DDB shows the shortcut arrow thingy
 
 then i linked to a PDF
 the PDF external file is about 60K and the DDB link file is
 about 6K which seems about right
 
 so what is up with the JPG case?
 
 BTW, the PDF pointer works fine, as does the
 JPG each launcing their own associated apps
 
 also
 can you expose the properties
 of the LINK ?
 i want to see the path that the link contains
 but it is blank in the right click
 properties dialog
 
 Dennis Saputelli
 
 Terry Creer wrote:
 
  Hi Dennis,
 
  See page 30 of the P99SE Handbook.
 
  Just right click in a DDB window and choose 'Link' from the menu (the menu
  that contains New, Import, Import Folder, Import Project, Link, View).
 
  Cheers,
 
  TC
 
  -Original Message-
  From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, 21 July 2004 10:31 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Shortcuts in 99SE ?
 
  in the 99SE DDB system (not the windows file system) it is not
  possible to add a shortcut (or link) to an external file, is it ?
  would a be nice feature
 
  Dennis Saputelli
 
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  2851 21st StreetFax: 415-647-3003
  San Francisco, CA 94110 www.integratedcontrolsinc.com
 
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 San Francisco, CA 94110 www.integratedcontrolsinc.com

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Re: [PEDA] was Shortcuts in 99SE ?

2004-07-21 Thread Dennis Saputelli

at the risk of beating a dead horse ...

i don't recall any mention in this list over the years
regarding the file description you can enter in the DDB
for a given internal file

don't know how i missed this and am finding it very useful

has anyone else seen this, use it, don't care about it 
or whatever ?

Dennis Saputelli

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Re: [PEDA] Board warpage?

2004-07-20 Thread Dennis Saputelli

you'll probably get a lot of different answers

150 deg F is not very hot, and this will probably help 
but still there will be stresses ...

since this bd is doing 'a very important job'
you may want to tread lightly

what is the measure of 'badly warped' ?

how big is the board and what is the shape?
ie long and narrow or what

how many layers ?
balanced construction internally?
parts on both sides ?

what is the cause of the warping?
it could be in the design, bare bd fab, or assy method
or some combination of all

was the board wave soldered at some step?
if not preheated properly and that can be one cause

keep us posted or put up a link to a pic if you can

Dennis Saputelli


Robison Michael R CNIN wrote:
 
 This email is not a Protel-specific question but instead concerns a
 generic problem with some boards I'm getting, so I apologize for being
 off-topic, but this forum has more PCB experience than any other I
 know of, so I would like to get your advice.
 
 A partner in a manufacturing effort is sending us full populated
 boards (ICs and passive components) that are badly warped.  We sent
 them back and rather than get the boards remade and repopulate them,
 they want to heat the boards up (fully populated) for three days at
 150 degrees Fahrenheit in order to straighten them out.  These boards
 perform an extremely important job and I'm worried about the stress
 on both the electrical components and the boards themselves.  Should
 I allow them to do this or should I demand the boards be remade?
 
 Thank you, Michael Robison
 

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Re: [PEDA] SOT-23 pinout

2004-07-16 Thread Dennis Saputelli

Ian Wilson wrote:
 
 On 02:15 PM 16/07/2004, Dennis Saputelli said:
 ..snip..
 
 BTW remember the To92's that were ECB ? (or was it BCE ?)
 just get out a bit of sleeving and your solder sucker and you
 were all set
 quite a bit harder to deal with in the case of SOTs though
 
 I have seem prototypes with SOT-23 upside-down with the gull-wing legs bent
 to meet the board.  It would have been done in a small production run
 except reverse pinned versions were available.  Worse think about this was
 that another design done shortly after suffered the *same* problem - I
 couldn't believe the lack of care and attention to detail.

same experience here
we were once given a job to make a few minor changes to a pcb already 
designed

NOT on the to-do list was to fix the SOT23's which were all wrong
and which we discovered by carefully manually checking things that 
were not supposed to need checking

when i pointed out this problem (and assuming i had it somehow wrong)
they said 'yeah those boards didn't work'  :}

ds



 
 Ian
 

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Re: [PEDA] SOT-23 pinout

2004-07-15 Thread Dennis Saputelli
and what is rule #2 ?  :}

personally, i oscillate between liking the 1 2 3 convention
and the E B C convention

like many things 'it's all bad'

i once had some T1 3/4 LEDs from HP
the short leg was the anode for that *particular* p/n
which is why they weren't very bright when installed

Dennis Saputelli

Mira wrote:
 
 Hi Dom,
 
 The basic numbering is
 
  3
 1 2
 
 However many other variants of the pinout exist out
 there.
 
 Rule 1: Always check the datasheet.
 
 Mira
 
 --- Dom Bragge [EMAIL PROTECTED] wrote:
  When you organise your footprints, what pinout do
  you use for SOT-23's?
 
  Do you organise the pins...
   -like shown in the attachment?
   -or with pins 23 reversed?
 
  The bigger question really is: Where do you derive
  your pin numbering
  guidance from?
 
  I find that some datasheets just show the pin names
  against the actual
  pins ( cutout the middleman of *numbers*) thus
  avoiding the issue
  altogether. This doesn't help those of us who want
  to be able to use a
  common footprint across multiple designs.
 
  One answer is define your own company standard,
  but if I chose
  against an industry standard, that'd be a bit silly
  wouldn't it.
 
  =
  Dom Bragge CID
  Snr PCB Designer
  Sydney, Australia
   ( 99SE sp6 )
 
  Find local movie times and trailers on Yahoo!
  Movies.
  http://au.movies.yahoo.com
 

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Re: [PEDA] SOT-23 pinout

2004-07-15 Thread Dennis Saputelli
when we say 'different pinouts' are we talking about the 
the geographical location of the given pin function or are we talking 
about the pin *number* assigned to the given geographical location ?
it makes a difference!

anyway what is clear from this dialog is that we all care about what 
we do and that there is no substitute for that care which can be
readily automated or completely provided by the CAD supplier
(vendors sell hot dogs in baseball stadiums)

it is a bit amusing that we probably get the xxx hundred pin thing
right but that the lowly 3 pinner often bites us 

BTW remember the To92's that were ECB ? (or was it BCE ?)
just get out a bit of sleeving and your solder sucker and you
were all set
quite a bit harder to deal with in the case of SOTs though

ds


Ian Wilson wrote:
 
 On 12:03 PM 16/07/2004, Mira said:
 Dennis,
 
 The pin numbering can only be 1 2 3.
 
 Mira,
 In Protel, pin numbers do not have to be numbers, they can be letters.  So
 you can use E,B,C for numbers if you want. If you have very commonly used
 parts making a matching set of Sch and footprints with matching pin numbers
 (using letters for both if that is better for you) makes good sense. One
 less thing to check.  The only downside to this is that you then have
 multiple footprints to manage if you ever decided to change you SOT-23 layout.
 
   The pin names
 might be 1 2 3 or E B C.
 I haven't seen transistors with different pinout but
 
 There sure are/were transistors, in SOT23, with different pinouts.  I have
 not seen them recently but you used to be able to buy reversed pinout
 versions of common transistors from Philips.  May well be obsolete now.
 
 Ian
 

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Re: [PEDA] Corrupted database

2004-06-02 Thread Dennis Saputelli

your ddb is probably ok
(we hope)
i have yet to have one go south

try deleting all your printers and reopening it

i have never had repair do anything either good or bad

i assume you have rebooted the machine somewhere along the way

next try deleting or renaming the .rcs file in \winnt

good luck and let us know the outcome

ds


[EMAIL PROTECTED] wrote:
 
 I have a ddb with a moderately complex schematic, and was just wrapping up an
 initial parts placement today in preparation for a meeting with the client
 tomorrow. I attempted to use the print preview manager to print to a PDF, but
 had various snafus along the way, mostly because I was trying to rush. Now, the
 preview is completely blank, and any time i attempt to open the PCB I get
 Access violation at address 028E9486 in module 'ADVPCB.DLL'. Read of address
 000F. I've tried turning off automatic compaction, performing a manual
 compaction (which appears to succeed), and performing a Repair (which also appears
 to succeed). But I'm no closer to seeing my PCB than I was several days ago.
 
 HELP
 
 Steve Hendrix
 
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Re: [PEDA] Router comparison

2004-05-26 Thread Dennis Saputelli
i was going to write this too
layer count of course effects cost

hole count has not been part of the cost matrix for sometime
unless you are making perf boards or something 

i like a board to look nice as much as the next person
but there's just not time anymore (there used to be more!)

and product cycles and rev spins are so frequent that
a lot of craft oriented efforts turn out to be just wasted time
i know because i've done it too often

of course the lines between functional issues and cosmetic issues 
are often blurry so the human router will still be around for a while

and Ian
i like PICs !
lots of mips for the buck and more and more on board stuff
everyday

Dennis Saputelli


Dom Bragge wrote:
 
  --- Mira [EMAIL PROTECTED] wrote:
  Autorouted boards in general have more holes, use more
  layers and this affects the price.
 
 It's been a long time (10yr) since more holes really affected the price
 (within extremes of course). I'd suggest that if an autorouted board
 took up more layers than a handrouted version, it wasn't done
 correctly.
 (i.e. I respectfully differ in opinion.)
 
  If your boss cares about saving some money from shorting the time for
  finishing the job and doesn't care about the PCB cost,
  then you must be working for a design bureau.
  You design the board once but it will be manufactured
  many times.
 
 I used to design a lot for long runs. Now much of my work is short
 order, as in I often only get only one panel's worth built. An
 autorouter is still a great investment. Saving a day or more of my time
 with an AR is worth it.
 
 =
 Dom Bragge CID
 Snr PCB Designer
 Sydney, Australia
  ( 99SE sp6 )
 
 Find local movie times and trailers on Yahoo! Movies.
 http://au.movies.yahoo.com
 

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Re: [PEDA] OT: Mentor PADS comparison

2004-05-19 Thread Dennis Saputelli

the 99SE autorouter is pretty good at yesterday's technology

if your board is largely through hole and DIPs and pin headers
and if the placement is reasonable it will route it in no time
and it will be largely usable

i seems to have hardwired code that recognizes those sorts of patterns

on bds using today's techology it is marginal or worse

as usual the answer is 'it depends'

Dennis Saputelli


Tom Robinson wrote:
 
 Is the autorouter in 99se sp6 really as bad as users make it out to be?
 
 I thought NeuroRoute was the 'cat's meow'.
 
 I remember years ago when it came out, a person who used it said they were
 'tickled pink'.
 
 tr :)
 
 -Original Message-
 From: Ian Wilson [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, May 19, 2004 9:55 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] OT: Mentor PADS comparison
 
 On 11:22 PM 19/05/2004, Protel Hell said:
 the perfect CAD does not exist, for one thing, for it to be perfect would
 require zero bugs and cost would be free, while DXP comes closer than most
 to the latter, it is also a leader in the former
 
 does anybody have a worse autorouter than Protel? or is not OK to mention
 that either?
 
 I actually have no problem with people complaining about Protel.  I would
 prefer it was not anonymously as this is sometimes used as a mask to make
 people braver than otherwise.  People generally tend to be more careful and
 considered in their comments when they can be identified.  I also really
 like it be factual and to be constructive.
 
 I think it is perfectly reasonable to point out where the program falls
 short of competitors.  The autorouter is a good example - it is being
 improved and some people are getting useful results, but I would be
 surprised if it was as good as the competitors and it is still quite
 slow.  I suspect my standard test board is just too hard - I will retry the
 P2004 version of the autorouter on something a little less challenging to
 see how it goes at some stage.  My Electra trial ran out (again!) before I
 could run this board through it.  (I may send it on to Pat Nystrom to see
 if he will run it through and send back the results - will you do that for
 me Pat?)
 
 Ian
 
 From: edsi [EMAIL PROTECTED]
 Reply-To: Protel EDA Forum [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Subject: Re: [PEDA] OT: Mentor PADS comparison
 Date: Wed, 19 May 2004 07:55:14 -0500
 
 PH
 Which CAD system are you used to working with?  I would like to hear
 more about your perfect CAD system.  Is it called Virtual CAD?
 
 
 Mike Reagan
 EDSI

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Re: [PEDA] Exporting DWG/DXF

2004-04-28 Thread Dennis Saputelli
not exactly sure what your last sentence means - copper pours?

what is the purpose of the conversion?

we do the export as primitives with square ends

we generally delete most of the layers incl:
top, bottom, pastes, solder, keepout and more
in the course of deleting all of that the copper pours go away

this leaves the layers:
outline, multi, topoverlay, maybe something else

after deleting most of the layers we do an explode ALL
in acad 2002

i think (but am not sure i remember this exactly) that acad R14 needs 
to do explode object by object
that would obviously not be acceptable

look around for a LISP program that will do explode all
in R14
there is something called BOMB and there are others
try
cadalog.com
for freeware lisp stuff

Dennis Saputelli


[EMAIL PROTECTED] wrote:
 
 Greetings the List,
 
 Our draftsman tells us that the multi-layer issue is not so much of a problem.  Our 
 real problem, it seems, is that when Protel exports a drawing (regardless of whether 
 it's in DWG or DXF format and regardless of whether it is exported as block or 
 primitives)he cannot explode the drawing into a useable format.
 
 He is using Autocad 14.  Is there any way to export drawings in a form where Autocad 
 can resolve it into a number of unfilled polygons?
 
 Thanx,
 
 Michael Badillo

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Re: [PEDA] PCB Crashes Protel 99SE

2004-04-26 Thread Dennis Saputelli
ideas:
uninstall your printer driver
or change the default printer driver to something else

i doubt that this is a license issue

or alternatively maybe it has something to do with loaded libraries

after closing protel and rebooting try moving one or both 
of these files
ADVPCB99SE.INI

CLIENT99SE.rcs

to some other folder
(they are in \WINNT)

i am pretty sure (not positive) that it will create these files if they
are not found

if it works you will have to set up some stuff again, but it's not too
bad

ds


Eccleston, Barry wrote:
 
 I am experiencing a problem when using pcb in 99se. The program crashes when
 I attempt to open a pcb file. It goes through the motions and gets as far as
 placing the tab for the pcb file, and then it locks up.
 The strange thing is that I can open the file ok when a colleague has a
 Protel database open on his machine. When he closes the database (with
 Protel still running) I cant open a pcb again.
 I am not an expert on networks etc, but I know we have a floating licence
 somewhere on the network. How can I find out the location of the licence?
 The person who installed the software originally no longer works here. On
 the security menu it states on pcb that access is granted for 2 users.
 Our IT specialist is baffled.
 I am using 99SE service pack 6.
 Has anyone got any ideas
 
 Barry

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Re: [PEDA] False DRC Clearance Constraint Error (99SE)?

2004-04-26 Thread Dennis Saputelli
i assume this is near a bd edge?

the bd outline and keepout don't necessarily need to be 
coincident

sometimes we either break the keepout in this situation (if the board is
routed)
or just bend it out a little to make the clearance

negative clearances don't work

Dennis Saputelli


Ray Mitchell wrote:
 
 Hello,
 
 I have a clearance constraint between a trace on the keepout layer and a
 component on the top layer set to 0mil (I've also tried -1mil) but it still
 gives me a DRC error between the keepout trace and the component pad that
 sits on top of it.  This is obviously not the correct approach. Suggestions?
 
 Thanks,
 Ray Mitchell
 
 Ray Mitchell
 Engineer, Code 2732
 SPAWAR Systems Center
 San Diego, CA. 92152
 (619)553-5344
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Re: [PEDA] Need more software

2004-04-17 Thread Dennis Saputelli
thanks
i took a very quick peek and i think AB Commander has it beat
i will tool around a little more later

Dennis Saputelli


Rusty Garfield wrote:
 
 Hi Dennis
 Try this one out. looks like old xtree gold. does ftp, zips files adds and
 deletes to zip exe files, double pane and more.
 Been using this for years on win2000 no problems.
 
 http://www.ghisler.com/
 *PS
 i rarely use Explorer anymore
 take a look at AB Commander as an alternative to Explorer
 http://www.winability.com/abcommander/
 
 it's not perfect but it's the best explorer replacement i have found -
 saves a lot of time when jumping around the hard drive
 saves favorites, recents and stuff like that
 
 Dennis Saputelli
 
 
 
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com
 
 
 Rusty Garfield C. I. D.
 Development Technician IV
 Sugar Land Product Center
 (281) 285-7611 (voice)
 (281) 285-7619 (fax)
 [EMAIL PROTECTED] (e-mail)

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Re: [PEDA] Need more software

2004-04-14 Thread Dennis Saputelli
i think all the files should always just go in:
My Documents
i suppose it could have sub directories of 
My Schematics  My FPGAs etc

:} only kidding but hey, it's good enough for MS !

seriously, i think something like John has proposed sounds 
reasonable
if i read this correctly then a zip could be expanded to recreate the 
structure easily on another machine

a lot of apps (most?) do pretty poorly at saving us drudge work
of routing around in the file dialogs when they could reasonably
guess where we might want to go or be

at the very least an app i think should propose at least initially to
do a Save As to the folder in which the file resides

this is not as obvious as it at first sounds when you consider that
the file (and app) may have opened by double 
clicking in Exploder *(TM)
so the app's file open dialog may not have been used
and be aware of where it is
Acad does a pretty fair job of figuring this out

*PS
i rarely use Explorer anymore
take a look at AB Commander as an alternative to Explorer
http://www.winability.com/abcommander/

it's not perfect but it's the best explorer replacement i have found -
saves a lot of time when jumping around the hard drive
saves favorites, recents and stuff like that

Dennis Saputelli


 Josie,
 
 Perhaps this makes a case for a firm DXP project folder structure (Altium
 standard), instead of just using the system default. Would make
 interoperability between tools a little easier as well.
 
 Many people have requested / touched on this issue before but now that DXP
 forces the use of projects it is time to start looking at a better method of
 file storage / destination folders.
 
 OK this is a pretty rigid approach, but so is project management really, so
 when considering this suggestion, do not think of it as barricades, but as
 auto file sorting.
 
 *Suggestion*
 
 Under project options an extra tab to select all these options would be
 nice, but not really needed, just some structure definition.
 
 The term system default below is not DXP default, but the default for open
 in any DXP dialogues seems to be the windows 'last open folder'
 default.
 
 First an extra tab in the project options folder to define the location of
 all libraries, which over rides the system default. Ok, you can do this in
 some way in the editors but the actual folder location should be fixed,
 leave the editor stuff to picking the libraries you want to use.
 
 The creation of a Project group name should auto create a /root folder.
 The prjgrp link file should be put here.
 
 An extra Tab in the Project options for USER setting the destination of the
 /root folder to over ride the system default should be available to the
 user..
 
 The creation of a Project should auto create a project name folder in that
 root /root/project/
 
 The project link file should stay in the /root/project/ sub folder, that way
 the whole project is self contained and you can just look in the /root/
 directory to see how many projects are there and what they are.
 
 As the project is self contained they are now also PORTABLE and a lot easier
 to perform Auto/Remote/Network backups  restores  of course compare whole
 projects.
 
 As the user creates a new file, a subfolder should also be auto created to
 place the files in, for the different  file types, like /root/project/schdoc
 or /root/project/exports
 
 As the user generates a new output type, a subfolder should also be auto
 created to place the files in, for the different  file types, like
 /root/project/cam or /root/project/reports
 
 Likewise when you ask to 'open' a file or project the default should
 automatically go the appropriate folder for the active group/project folder
 first, or in the case of new projects, the group root folder.
 
 If files are imported to the project, and do not belong to a file group, a
 copy of the imported files should be auto copied to a /root/project/file
 type folders first then the /root/project/imports folder if the file type is
 not assigned (documents, PDF...). They can always be deleted later.
 
 With the exception of the next point, the above is not a big deal, it is
 merely looking up defaults, very little to leave to chance, and elimination
 of error or just saving time is a good thing right?
 
 The view / structure of these files/folders should be followed in the
 Project browser window in DXP.
 
 ##
 
 The ODB++ standard defines a structure for file sorting, perhaps we need a
 DXP file structure standard.
 
 Do not know about others, but I detest playing 'hunt the file' games, or not
 knowing what files are linked to what projects as it uses link files. The
 file structure and project structure should be 'self contained' or self
 explanatory, with or without DXP open.
 
 Best Regards
 
 John A. Ross
 
 RSD Communications Ltd
 8 BorrowMeadow Road
 Springkerse Industrial Estate
 Stirling, Scotland FK7 7UW
 

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Re: [PEDA] Good schematic/PCB development suite recommendation?

2004-04-11 Thread Dennis Saputelli
so as a friend of mine once said:
'you got any _good_ news'?

our 2004 has still not arrived
i was advised by altium that the CDs were 'injected' into 
the US mail system in mid march
(i'll leave that comment as the straight man setup line)

it has been a long long stated goal of protel to offer
a complete suite of end to end design tools - 
way back to the earliest days when they weren't really offering them

so i guess this latest push into FPGAs et al is the final 
leg of that journey

PCB layout tools are maybe just not sexy enough to hold their full
attention any longer

a solid 3D modeller (2-way w/ solidworks), 
a real (useable) interactive semi automated
comp placement tool and
a screaming -interactive- autorouter
would be examples of a few productivity enhancers that would 
be much appreciated by us board guys
these types of enhancements don't seem to be on their radar

however, the multi channel stuff is compelling enough for 
us to give 2004 a whack
also in a few years 99SE will probably finally break due to some
Access/MDAC or other MS problem, so the switch over is an inevitability
i think

Dennis Saputelli

edsi wrote:
 
 The problem with DXP, it is fairly widely acknowledged, is that its
 increased power has come with an increased complexity which has not yet been 
 sufficiently been compensated by ease-of-use enhancements. An
 experienced 99SE user is going to face a serious retraining hit at this time. The 
 general report from those who bite the bullet and learn the DXP way is that it is 
 worth it, *but*, quite obviously, if you are going to have to retrain, the time is 
 ripe to consider other systems.
 
 Here is my assessment
 Fair Warning ... don't uninstall your 99SE if the EULA indeed recommended that you 
 uninstall. I have had 2004 long enough to do about 6 pcb designs, and can report few 
 if any real improvements. Let's count the real improvements, without arguing whether 
 features are better or not. PCB onlyI don't dabble in the schematica world
 
 SPECTRA interface has improved, ODB output is an improvement, PAD stacks are finally 
 implemented. RELIABILTY rates with version 3.x. I got access violations to the point 
 that it quit working on me completely. Had to shut down for a half day, translate 
 that to half day loss wages. Mouse control rates with version 3.x . Things stick to 
 your cursor and you scream at your PC LET IT GO , I don't want to pick that up. 
 Maybe I need to slow down my inputs so DXP can catch up. I forgot to mention, it 
 worse than a resource hog it is a pig. It is slower than 99SE. I am running a 2 Gig 
 machine. I had to disable MACAFEE virus and my firewall. Half the time it wont even 
 come up if the firewall is activated. How is that for real feedback and not just 
 saying it sucks. Some Keystrokes are disabled so now you have depress buttons with 
 the mouse/ cursor which slows design down,  it has the real feel of ACCEL.  I also 
 am trained on PCAD.Most the menus are not easily legible, you have do read thru
 alot of uneccessary inform
 ation and  pictures to change one parameter. The same information is there but the 
 presentation is poor. Maybe a PADS user or an ACCEL user might like it because they 
 don't know the difference. ACCEL graphics looks like bit-mapped Crayola and if you 
 zoom out in PADs round pads turn to squares and other objects , so this looks good 
 to new Altium customers.
 
 The masking features are cool but in case ya'll didn't know it, you could mask in 
 99SE. In single mode, with one a mechanical layer click on the net, net class etc. 
 on the pcb panel. The mask isn't crystal clear, but Protel could have improved this 
 without introducing ACCESS VIOLATIONS , Bet you didn't know you mask in 99SE. I've 
 been doing it for years to analyses complex routes.
 
 99 percent of what I typed into the online help turned up no help. Custumizing is 
 very limited.   I exceeded this program's abilty in a few hours.  I exceed the 
 original DXP release in about 30 minutes. It was useless. I must be getting smarter. 
  2004 is much better than DXP but ...
 
 There is no real clear advantage over 99SE PCB other than popping up ACCESS 
 VIOLATIONS . It designs the same  boards, in more time . Believe me, by the time I 
 rolled my 6 th board out, I know how to use this program. It takes longer to design 
 with because you fight with it instead of it rolling off your finger tips. I don't 
 care if Altium is listening or not at this point, Im just passing the costs on to my 
 customers like everyone else does. Hope Altium never needs a design from me because 
 I would charge them my highest rate. At this point, I don't have time to debug their 
 tools anymore, including their router. This stuff should be mature, very mature. It 
 has been under development for a long time. DXP is basically on it 4th release with 
 2004. I don't see the dust settling until SP2 for 2004. I will be closer to 
 retirement by then so it won't

Re: [PEDA] Are fiducials necessary?

2004-04-10 Thread Dennis Saputelli

do you really mean suggested to remove ?

i would think that in the context of a license agreement
this would be a possible requirement to remove (which is a common term)

licenses aren't about making suggestions 

so the question is not the practical question of whether they can
coexist or run at the same time as a practical matter
but whether their is a requirement on their part that we remove 99SE

the acad license has a requirement to remove and destroy any previous
versions

ds

Tony Karavidas wrote:
 
  -Original Message-
  From: Steve Wiseman [mailto:[EMAIL PROTECTED]
 
 clip
 
  (I wonder if that's still the case in 2004 - my copy just turned up.
  Reading the license suggested that I'd have to remove my copy of
  99SE, and I'm damned if I'm doing that, so time for a chat with the
  distributor and Altium, I guess).
 
  Steve
 
 You can keep 99SE and 2004 on the same machine (and even have both open at
 the same time)
 
 Tony
 

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Re: [PEDA] REMOVE 99SE? was - Are fiducials necessary?

2004-04-10 Thread Dennis Saputelli
we should have changed the SUBJECT, sorry
Dennis Saputelli


Tony Karavidas wrote:
 
  -Original Message-
  From: Steve Wiseman [mailto:[EMAIL PROTECTED]
 
 clip
 
  (I wonder if that's still the case in 2004 - my copy just turned up.
  Reading the license suggested that I'd have to remove my copy of
  99SE, and I'm damned if I'm doing that, so time for a chat with the
  distributor and Altium, I guess).
 
  Steve
 
 You can keep 99SE and 2004 on the same machine (and even have both open at
 the same time)
 
 Tony
 

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Re: [PEDA] Protel 99SE - Routing vias are all 20mil diameter w/28mil hole!

2004-04-09 Thread Dennis Saputelli
the spectraa router?
as far as i know it always comes back w/ 28 holes
pretty easy to fix if you don't forget, but somewhat bush league

the 99SE router only uses the board via and i haven't seen it trash the
hole size
there are 3 candidates for sizes for a given type have you checked all 3
size pairs?

mike i think has said this is fixed in P2004 re spectraa

Dennis Saputelli

Ray Mitchell wrote:
 
 Hello,
 
 In my design rules I've specified that all routing vias are to be 20mil
 diameter with a 10mil hole.  However, the router makes them all 20mil
 diameter with a 28mil hole.  Nice feature!  I know it hasn't always done
 this - only sometimes.  I only have one design rule for routing via
 style.  Its scope is Board and it is enabled.  Am I holding my mouth
 right for some routes and wrong for others?
 
 Ray
 
 Ray Mitchell
 Engineer, Code 2732
 SPAWAR Systems Center
 San Diego, CA. 92152
 (619)553-5344
 [EMAIL PROTECTED]
 

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Re: [PEDA] Good schematic/PCB development suite recommendation?

2004-04-09 Thread Dennis Saputelli

ditto this snip below for us
and we haven't gotten 2004 yet either
although we did the access code in the mail
and that was over a week ago

 I went back to Protel and made the transition from 99SE to DXP. I don't
 know why they didn't just fix 99SE instead of basically starting over.
 Trying to use DXP at first made me feel like a complete idiot, it is a
 resource hog (my 1GHZ computer is too slow?) and the software still
 isn't quite finished (I am still waiting for 2004, hopefully it is
 better).  This has been very painful, but at least it wasn't $40k a
 seat!

at $40K  you can get a pretty nice car wrapped around a seat

PADs charging for the copy/paste *is* pretty outrageous

do they charge for mouse support or file save as too?

Dennis Saputelli


Cliff Gerhard wrote:
 
 Bill, I think your opinion about Mentor is spot on.
 
 Sorry long rant ahead
 
 A few years back, I took a job managing the layout department (among
 other things) for a company that had been using PADs for several years.
 One of my jobs was to pick new CAD software because they were very tired
 of PADs.  The one that really got me was when I asked PADs about cutting
 and pasting.  I had an op amp circuit that was similar to one that we
 had done on another board.  I wanted to copy it to the new design.  It
 would only copy the components.  All of the traces would be removed.
 They came back with you need our design re-use package.  $4k +
 Maintenance to cut and paste! Unreal!
 
 We had also been bitten several times by software bugs (DRC and Gerber
 generation) that caused very expensive and time critical boards to be
 scrapped.  I was personally using Protel at the time, but it was not
 even considered because they wanted a high end tool.
 
 We were using Cadence for IC development (well into six figures for
 those tools!) and I was under some pressure to pick the Cadence PCB
 tools. All of the engineers (about 20) were using OrCAD (which had just
 been bought by Cadence) and we didn't want all of the engineers to have
 to learn a new schematic capture program, so we also needed to be able
 to use OrCAD as a front end for a while at least.
 
 The tools from Cadence and Mentor were not well integrated at all at
 that time.  They had both been gobbling up smaller companies and adding
 bits and pieces to their software into their existing products.  Many
 different and non-intuitive ways to do the same thing.
 
 I did my research and it was very much like dealing with used car
 salesmen. A very unpleasant experience.  At the time, Mentor had just
 picked up Veribest and their interactive manual routing was very
 impressive.  We had to maintain all of our old PADs designs and both
 salesmen (Cadence and Mentor) assured me, in writing, that they had a
 working PADs translator and it would not be an issue.
 
 I made the decision to go with Mentor. The cost was about $80k for two
 seats.  We immediately had problems.  The PADs \translator was non
 functional for quite some time and we had a bunch of problems trying to
 use Orcad Netlists.  You had to have an error free netlist loaded to
 even place a part on a new board!
 
 Once we placed the P.O., we needed support to get through these issues.
 Tech support and the leghumping salesman, who had been calling me
 several times a day prior to getting the P.O. signed, were now taking
 days to return my calls.  At one point, I feared that I might loose my
 job over the decision.  After about a year (no exaggeration) the layout
 people were finally getting up to speed with the tools and fairly happy
 with them.  These were very sharp people and excellent designers too.
 
 I have since moved on and am now back with a small product development
 company.  I was again faced with the problem of choosing a CAD system.
 We do not have the deep pockets to afford the high end tools.  After
 my experience with Mentor, I am not sure I would have considered it even
 if we could afford it.
 
 I went back to Protel and made the transition from 99SE to DXP. I don't
 know why they didn't just fix 99SE instead of basically starting over.
 Trying to use DXP at first made me feel like a complete idiot, it is a
 resource hog (my 1GHZ computer is too slow?) and the software still
 isn't quite finished (I am still waiting for 2004, hopefully it is
 better).  This has been very painful, but at least it wasn't $40k a
 seat!
 
 I hope Protel is not bailing out of the shrink wrapped CAD market.
 There isn't much else out there for us who can't afford (or don't need)
 the high dollar tools.  If they are putting all their eggs in the
 embedded system business I can't see them surviving too much longer.
 Then I guess I'll be back to that familiar place of having to pick a new
 CAD system.
 
 o~o
 Cliff Gerhard, P.E.
 E-M Designs, Inc.
 
 
 -Original Message-
 From: Brooks,Bill [mailto:[EMAIL PROTECTED]
 Sent: Friday, April 09, 2004 12:48 PM
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA

Re: [PEDA] Strange problem with PCB library 99SE

2004-04-02 Thread Dennis Saputelli
we don't normally work this way (lib internal to project ddb)
so i am not positive
but did you do the Add libs thing (button in browse libs) ?

ds


 Terry Creer wrote:
 
 Greetings all,
 
 I'm having this strange problem with a project I'm working on. I have
 the PCB library inside the same database. I go into a PCB document and
 share that library and a lot of the components do not show up in the
 library browser window. In order to view all of the components, I have
 to export the library out of the database (either into another
 database or just as a lib file). What gives? Any Ideas? I can't
 remember this ever happening before...
 
 Cheers,
 
 Terry

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Re: [PEDA] 2004 getting fired

2004-03-30 Thread Dennis Saputelli
what happens if you place the parts on the pcb before the 
netlist load?
won't it match up the designators?

how come you don't post in the DXP forum?
altium might listen to you there more

Dennis Saputelli

edsi wrote:
 
  I might get fired  for any more errors  2004  makes.  I had previously reported 
 that loading a netlist was troublesome,  I can now report that it is also very 
 unreliable.
 
 On two previous designs, 2004 would not load 0603 components without the library 
 opened.  On a new  design I have  two parts that will not load even if the libraries 
 are opened.   IT flat out will not load the components.I confirmed there are no 
 problems with my netlist, or libraries by creating a ddb file in 99SE.  The netlist 
 loads flawlessly in 99SE.  What's up Altium?  I can get fired for errors like this.
 
 Mike Reagan

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Re: [PEDA] reg hole on PCB and library

2004-03-29 Thread Dennis Saputelli

1]
i wouldn't worry about not seeing the 
hole as long as it is the drill file

2]
no there is no way and it really is a shame

Dennis Saputelli


Paresh Pai wrote:
 
 Hi everybody.
 
 I am facing the following problems in 99SE
 
 1. I have designed a single sided PCB for a microcontroller programmer. It has a 
 7812 regulator chip which is to be soldered and also fitted to the PCB (using a 
 small nut), so that the PCB ground copper acts like a heat sink. To do this, I have 
 placed a rectangular copper fill with a hole in the center and aligning the hole 
 with that of the 7812 (TO220 package).To generate the hole I placed a 
 pad(multilayer) and adjusted its hole size to be equal to X-size and Y-size (all 100 
 mil).But when I generate a print preview by using following settings, I do not see 
 the hole in the copper fill. The whole copper fill appears as black.
 The settings I use are :
 
 Include Top side
 Include bottom side
 Include double sides  all are selected(checked)
 
 Show holes ..selected(checked)
 
 Color set... Black  White
 
 The layers selected in the preview are
 Bottom layer
 Keepout layer
 Multilayer
 
 Can anybody help me to find the hole ?
 
 2. My second problem is regarding libraries.
 When I load a new schematic, is there any way to know the  library from where  each 
 component was taken by the designer of the schematic ? If you double-click on a 
 component , it shows the library reference,footprint etc.  but the library is not 
 known. Similarly in PCB editor, it shows the footprint etc. but the library is not 
 shown.
 
 Thanks in advance.
 
 Paresh Pai
 

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Re: [PEDA] Data line transformers (was: Antenna coil)

2004-03-28 Thread Dennis Saputelli
yes pls keep us posted
would love to see an AES app


Brian Guralnick wrote:
 
 My first test PCB printed with data line transformers is coming next month, no 
 electrical connection from A side to B side.  Is anybody interested?
 
 Capabilities:
 Get over 500 megabits from 1 side to the other.
 Perfect phase clock drivers  inverters.
 
 Great for isolating SPDIF/AC3/DTS audio signals, Ethernet line transformers, cheaper 
  smaller than optocouplers, faster by a long shot, analog signal mixers and more...
 
 Slow speed signals need only a 2 layer PCB, high speed need 4 layer.  Also, 1 PCB to 
 the next with gap sizes typically under .2 inch. (this is for super high voltage 
 separation, in the 5-50KV and above when PCBs edges are coated.)
 
 _
 Brian Guralnick
 

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Re: [PEDA] 2004 Global edits

2004-03-27 Thread Dennis Saputelli
you should post your experiences to the DXP forum as well as here

Dennis Saputelli


edsi wrote:
 
 Tony wrote
 Maybe Altium could implement a few more global dialog boxes for us to have
 high level, quick functionality like the T,I,P box. (Component Text
 Position
 is what it's really called)
 
 Tony
 I agree and more..  the inspector panel is better than the first DXP release but is 
 far from polished  For example if you select a few random components and look at the 
 inspector,
 it shows in blue  NAME and Component Comment.   If you accidently  click on either 
 one of these two it goes wacky and arbitrarily picks one component.  If you  click 
 on somewhere in the panel it  toggles
 between reading  the words NAME and component .   Both  are the same word as REF 
 designator. Which by the way is the correct name and never used. It's just 
 illogical behavior.   What is the meaning of this? We had a President here in the 
 USA  that tried to parse the word isIs Altium parsing  the word NAME? It 
 has a wacky, non logical feel to it.
 
 Off topic
 Can anyone tell me what the other silly   choices  ie  Standard, mechanical, 
 graphical, NET TIE have to do with my component?   It looks like another PCAD   
 migration.  What is it?  These options are in the inspector.
 
 I am starting another PCB   board thank you, This is the second board that 0603 
 components will not import without the library being opened.  I experienced this 
 before wanted to confirm the problem was not me.  I am convinced there are now two 
 bugs with  loading netlists.  In case Y'all didn't notice,  in 99SE components 
 which began with zero like 0805 and 0603 would sometimes shorten by dropping the 
 leading zero's.   It didn't happen all of the time but I know how to reproduce it.   
  I think there might be something related to the dropping the leading zero.
 
 There are a few other problems with netlist loading.  Including two things that must 
 be applied.   Dont you hate to install Bill Gate's crap and all the questions are  
 hit any key to continue otherwise  it is Good Gye.  Just freaking finish the 
 install, we already established I what I want to do. Loading a netlist requires you 
 to always check this same little box ADVANCED MODE. Then it always asks the same 
 silly question.. do you want match the reference numbers?.  WAIT did I say reference 
 numbers,  this the first place 2004 uses the word REF Number then it never uses it 
 again.  This part was programmed by a subcontractor . I am sure of that.
 The most annoying part of the netlist load is the poor report.  It fails to give you 
 a comprehensive report of what does not get loaded.   The report only contains ref 
 designators   and the word NO ACTION.  No kidding ,   I know it was no action.  A 
 comprehensive report with part information (starting with footprint) would help me 
 find out exactly what went wrong.  So tonight I have two pages of reference numbers 
 that I am manually writing  next to them, my footprints.   Oh how cool, I am using a 
 Pencil for something that was automatic in every version up to DXP.
 
 I hope Altium still feels that PCB is part of their long term plan,  The package has 
 alot to offer,   There are things I am dying to try out but PCB is taking up more 
 time because the ball was dropped on a few things including loading netlist. So I am 
 spending time learning to use my pencil instead of using the advanced features.
 
 If you u haven't tried the Autorouter,   Don't .  It still doesn't work. I have 
 baselined a BGA design with 2000 components against 2004,  Spectra and ConnectEDA, 
 Electra.  2004 sputtered for 2 hours and on the the third hour crashed.  That is 
 really sad.  They should take the router off this product and not even offer it for 
 sale.
 
 Mike Reagan
 EDSI

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Re: [PEDA] Advanced PCB / Advanced Route 3.0

2004-03-20 Thread Dennis Saputelli
what i remember is that it would honor the lock if the 
preroutes were 100% complete for any given net

Dennis Saputelli


matt wrote:
 
 wasn't there a bug in advanced route 3.0 which prevented this from working ?
 I seem to recall (although not quite sure) some version having this problem
 of ignoring the lock and routing from scratch everything no matter what had
 been locked.
 
 - Original Message -
 From: Joe Sapienza [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Saturday, March 20, 2004 11:47 AM
 Subject: Re: [PEDA] Advanced PCB / Advanced Route 3.0
 
  I believe that If I remember correctly and I understand your question, all
  you need do is select to lock all pre routes and then run the autorouter.
 
 
  - Original Message -
  From: Jim Labrecque [EMAIL PROTECTED]
  To: Protel EDA Forum [EMAIL PROTECTED]
  Sent: Saturday, March 20, 2004 11:36 AM
  Subject: [PEDA] Advanced PCB / Advanced Route 3.0
 
 
   I realize I am using old software, but it is all I have on hand-
  
   Does anyone know whether it is possible to manually lay down some tracks
   in Advanced PCB, and then have Advanced Route recognize these tracks
   when you open the design?
  
   What I am trying to do is some incremental routes with advanced route-
  
   For example, the first routing I am trying is to have Advanced Route
 route
   all of the voltage/gnds.  This is a multilayer design with 4 planes
  consisting of
   3 voltage and 1 ground.
  
   I route the 3 voltages and grounds and then export the design back to
  Advanced
   PCB for some cleanup- (ie shortening some of the stubs and adding
  additional
   pads for connection into the plane on high current parts).
  
   I then save it so that I can import it back into Advanced Route and
 route
  the
   rest of the signal tracks.
  
   However, after the design is loaded into Advanced Route, any additional
  tracks
   or pads that I have added are not in the design-
  
   Anybody have any ideas or suggestions?
  
   Thanks, Jim
  
  
  

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Re: [PEDA] Advanced PCB / Advanced Route 3.0

2004-03-20 Thread Dennis Saputelli
it doesn't sound like you have a netlist, do you?

so while we are strolling down memory lane ...
how about MAXROUTE ? 
had a protel interface and
would only run on windows 2.0 (win 3.0 was too advanced)

fortunately you could quit win 2.0 and it would drop
back to the good 'ol DOS prompt where you could get some
actual work done

Dennis Saputelli


Jim Labrecque wrote:
 
 The problem is that the preroutes aren't even recognized by Advanced PCB-
 
 Another example-
 
 If I take the PCB design in Advanced PCB and draw a square out of a series
 of tracks on the top layer and then import it into Advanced Route-  Advance
 Route doesn't see the square- (what I mean is that physically is not there.  It
 is as if I never placed any tracks).
 
 I appreciate all the responses.
 
 Thanks, Jim
 
 - Original Message -
 From: Joe Sapienza [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Saturday, March 20, 2004 11:47 AM
 Subject: Re: [PEDA] Advanced PCB / Advanced Route 3.0
 
  I believe that If I remember correctly and I understand your question, all
  you need do is select to lock all pre routes and then run the autorouter.
 
 
  - Original Message -
  From: Jim Labrecque [EMAIL PROTECTED]
  To: Protel EDA Forum [EMAIL PROTECTED]
  Sent: Saturday, March 20, 2004 11:36 AM
  Subject: [PEDA] Advanced PCB / Advanced Route 3.0
 
 
   I realize I am using old software, but it is all I have on hand-
  
   Does anyone know whether it is possible to manually lay down some tracks
   in Advanced PCB, and then have Advanced Route recognize these tracks
   when you open the design?
  
   What I am trying to do is some incremental routes with advanced route-
  
   For example, the first routing I am trying is to have Advanced Route route
   all of the voltage/gnds.  This is a multilayer design with 4 planes
  consisting of
   3 voltage and 1 ground.
  
   I route the 3 voltages and grounds and then export the design back to
  Advanced
   PCB for some cleanup- (ie shortening some of the stubs and adding
  additional
   pads for connection into the plane on high current parts).
  
   I then save it so that I can import it back into Advanced Route and route
  the
   rest of the signal tracks.
  
   However, after the design is loaded into Advanced Route, any additional
  tracks
   or pads that I have added are not in the design-
  
   Anybody have any ideas or suggestions?
  
   Thanks, Jim
  

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com



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Re: [PEDA] 2004 DXP Looks Great but lost features

2004-03-18 Thread Dennis Saputelli

in 99SE you don't need any specific lib opened to load a
netlist
we often use orcad netlists wher NONE of the footprints match any names
that we
will use

in that case we just place them as we see fit and the netlist load
succeeds 
without a perfect match 
this is an appropriate working method at times

ds


Ian Wilson wrote:
 

 Doesn't P99SE have the same issue.  You have always had to have the source
 libraries loaded (not opened).
 
 If a library is not loaded in the library list the component will not be
 loaded.  The difference is that DXP and P2004 allow you to specify exactly
 which library it should come from and there is none of that silly XREF
 substitution that P99SE and older could get up to.  I *love* the strict
 library management of DXP.  Going back to the Just grab it from the first
 lib in the list that has the same footprint name just doesn't cut it for
 me.  I want full control.  The thing I find irritating, a bit, is that if I
 *fully* specify the source library when nominating the footprint, should I
 really need to have that library loaded in the Library panel? Surely it can
 go fetch.
 
 Ian
 

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Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Dennis Saputelli
this is a great picture Ian!
i totally agree with your statements here

we have found the smaller footprints to be both more reliable
and easier to assemble
a large pad deposits more paste than a smaller pad (-duh!)
this, in excess, is one of the main causes of tombstoning

and the huge silkscreen outline accomplishes little
except maybe it makes a tiny profit for ink vendors :)

we have NEVER been able to use protel supplied footprints
for this reason alone

as to maximum packing density:
isn't this a function of the placement jaws?
and isn't that a moving target?

what are good numbers for 0603 for example?
side to side and end to end?

i have no experience w/ SMTPlus
i assume they know what they are doing and i have heard only
good things about them
but since we can't get native protel footprints it greatly 
lessens the appeal for us

when you say wave solder
are you referring to bottom side parts which are glued and
then waved?

regardless of the pad size and in our somewhat limited 
experience with this process (glue, flip and wave)
it has been less satisfactory than a fully reflowed process

Dennis Saputelli

Ian Wilson wrote:
 
 One to stir up the hornets nest a little...and a little off topic maybe
 
 http://www.considered.com.au/ProtelFiles/images/Phycomp_vs_IPC.gif
 
 shows the Phycomp (the old Philips, now part of Yageo) reflow 0402
 footprint versus the 0402 footprint from the Altium P2004 Chip Resistor
 library (in the ../Library/PCB folder) which I think is based on IPC.
 
 You can see the ridiculous difference.  The one on the left is based on
 reflow with a +/-0.15 mm placement accuracy.  I need maximum packing
 density - IPC in this case is not on for this application.
 
 The problem with one size fits all (and an oversize like the IPC postage
 stamp footprints) is that assemblers and others can grab onto it as a
 pseudo-standard and say we only accept IPC footprints.  Instead of
 attempting to understand the pressures on the product and adapting
 processes they simply take the easy way out.  Sure, using small footprints
 may reduce yield and increase costs - in some applications this is
 appropriate.  By *blind* use of overgenerous footprints I think designers
 are loosing the ability to optimise their products globally - they are
 reduced to local optimisation only.  And yes, this is probably a skill that
 is developed over time and with experience - but newcomers to the industry
 should be told, in no uncertain terms, that IPC footprints are an
 appropriate starting point and since they are designed to cope with many
 soldering processes are necessarily not optimum for any..
 
 I am not keen on any library that thinks wave footprints are the same as
 reflow.  Does SMTplus makes the distinction?
 
 Ian
 

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Re: [PEDA] Protel 99SE crashes when Printing PCB

2004-03-12 Thread Dennis Saputelli
I have definitely seen what Ivan says
HOWEVER
in my experience all such crashes were SCH and not PCB
which i believe was the user's problem

Dennis Saputelli


Bagotronix Tech Support wrote:
 
 If it's a networked printer, I've seen Protel crash when trying to print to
 a non-existent (or not properly configured for sharing) network printer.
 IIRC, it was a HP printer that wasn't visible on the network that caused the
 crash.
 
 Best regards,
 Ivan Baggett
 Bagotronix Inc.
 website:  www.bagotronix.com
 
 - Original Message -
 From: Brian Guralnick [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Friday, March 12, 2004 4:42 PM
 Subject: Re: [PEDA] Protel 99SE crashes when Printing PCB
 
  Ohhh boy, this is an oldy.
 
  I cant remember what was done to fix the problem, but, if you search the
  [PEDA] archives for printer driver  crash, you will find a bundle of
  issues.
 
  I do remember that Protel had some problems with true post-script thru
 laser
  printer drivers.
 
 
  1 fix I remember was to delete all your printer drivers from the control
  panel  install this win-PDF printer driver from:
 
  http://www.daneprairie.com/
 
  After loading / printing to pdf / saving you project, re-install your true
  printer driver  Protel should stop crashing when printing in the future.
 
  _
  Brian Guralnick

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Re: [PEDA] SMTPlus Common PCB footprint specifications

2004-03-11 Thread Dennis Saputelli
we looked at SMTPlus
but as i understood it, they don't do protel

did you have to create the footprints from dwgs?

Dennis Saputelli


Frances Wheeler wrote:
 
 I have been using SMTPlus for years for footprints
 http://www.smtplus.com/  they have the expertise and my customers have
 always been pleased with the production results. They will develop a new
 footprint quickly and get it back to you the same day. Check it out they
 have saved me lots of time and therefore lots of money.
 Fran
 
 -Original Message-
 From: Leo Potjewijd [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, March 10, 2004 5:24 PM
 To: Protel EDA Forum
 Cc: [EMAIL PROTECTED]
 Subject: Re: [PEDA] Common PCB footprint specifications
 
 At 10-03-04 18:36, Ray Mitchell wrote:
 I'm sure this is a repeat, but is there a simple specification readily
 available that gives the commonly accepted (if there is such a thing)
 
 dimensions for 0402, 0603, ..., SIOC-14, etc., and all the other
 standard footprints?  I don't really want to wade through a bunch of
 technical stuff to derive all of this myself and I certainly don't want
 to
 trust a priori the patterns that come with Protel or any other
 product.  It's really annoying when part manufacturers don't provide
 these
 footprints, assuming they are common knowledge.
 
 Others have already refrenced the s'standards' (IPC). I'm a little more
 sceptical.
 
 To my knowledge, there is no such thing as a standard footprint.. Was it
 not the CEO of Sun Micro Systems who said at one time I just LOVE
 standards, because there are so many of them.
 
 In short, even a simple shape such as a 0805 is implemented differently
 by
 different manufacturers.
 Weird? I'd say so. Surprising? Not really: OUR wheel is MUCH
 rounder.
 New and improved.. New formula..  You know the buzz.
 
 I use a spreadsheet (not ready for the public yet, but I'll post it
 sometime in the not-so-distant future to the Yahoo list) to calculate a
 footprint from the dimensions and tolerances of the component given by
 the
 mfgr. The differences are sometimes quite large (as in: HUGE); in fact
 so
 large that a component from anoher  mfgr will not fit  on the same
 footprint (we lost a complete production run on that one).
 
 I'd still say to look up the mfgr datasheets (whenever available) and
 derive your own footprints from that information using a combination of
 guidelines (IPC, JEDEC) and common sense, seasoned with a tuch of
 practicality (you don't want 73 mils distance on 0805 pads when you're
 using a 5 mil grid).
 Hey, I even round off pad sizes that were designed in mm to an integer
 number of mils.and I'm in the metric part of the world ;-) Find
 values (IPC, JETEC, your own fab house) for things like placement
 accuracy, heel and toe solder fillets and ask your board stuffer what
 component clearances (and directions) are needed for what processes and
 machines they use.
 All of these (and then some) will influence the final optimum
 footprint.. Last but not least: small series (50+) can most of the
 time get away with
 minor deviations from optimum, big series (500+) usually can not, huge
 series (10k+) never can.
 
 A lot of work, yes, but one only uses so many different components..
 
 I found it worthwile to invest the effort: I have no production failures
 
 yet on my boards (apart from that one that was designed for Philips TSOP
 
 and could not accomodate Fairchild).
 BTW, I am designing boards for just 10 years now, so I really don't know
 
 much about the subject yet. In fact, I'm still learning, every single
 day.
 
 To qoute another frequent poster to this list: I hope this helps.
 
 Regards,
 
 Leo Potjewijd
 hardware designer
 Integrated Engineering B.V.
 
 [EMAIL PROTECTED]
 +31 20 4620700

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Re: [PEDA] 2004 DXP Looks Great,

2004-03-09 Thread Dennis Saputelli
Phil's comments pretty much sum up our findings, feeelings 
and experience too (except we never did Mentor)

after a few whirls around our DXP is 'still in the box' too
there's just never any time to lose getting up to speed and 
messing around with new ways of doing the same thing

Dennis Saputelli

DUTTON Phil wrote:
 
 Bill,
 
 You've hit the nail on the head.
 I've used Protel since 1987, I've also used Mentor.
 I was influential in converting my current company from using Mentor to
 using Protel.
 Simply because, for our kind of work, Protel was more intuitive, faster,
 and the designer could focus on designing the board. My DXP is still in
 the box. My current workload cannot tolerate the learning curve or
 reduction in my efficiency to change to DXP at this time. There are some
 good things in DXP, but there are many features that really don't seem
 to help my productivity.
 
 regards,
 
 Phil Dutton CID
 

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Re: [PEDA] Protel ceashes (EX: Vias do not tent when expected)

2004-03-06 Thread Dennis Saputelli
my 2 cents on this
i think this topic is on topic
by elimination i would say ATI on-motherbd video is next suspect

FYI and not pertaining to your crashes the latest stuff i have 
read in PC magazine says that defragging doesn't do much good
might do a little harm in the sense of the risk of rewriting everything

is this machine targeted at CAD users or general office use?

would love hear what the final solution is

Dennis Saputelli


Leo Potjewijd wrote:
 
 I'm not sure this still belongs on the PEDA forum But I'm sure to be
 corrected if it doesn't.
 
 At 06-03-04 00:03, Abd ul-Rahman Lomax wrote:
 snip-snip
 Because Protel99SE.exe has caused errors and will be closed.
 
 My condolences.
 Thanks
 
 snip
 First of all, the virus scanner and network differences are not likely to
 be the cause, in my opinion. Rather the most likely causes, at least the
 ones I'd first suspect, are the video card or a memory problem, i.e., a
 bad chip. There are video cards known to cause Protel to crash ATI
 cards were famous for this. And a bad memory can cause, of course, all
 kinds of problems. Sometimes they will only show up with one program that
 happens to be vulnerable. As far as the bad memory possibility is
 concerned, I'd swap around memory devices, if possible, or at least run
 some very thorough memory test utilities, the kind that you let run all
 night
 On the 'old' machine at work (the one that took out 7 Ddb's in one crash) I
 use a Matrox Millennium G450 (32MB) videocard that was purcased especially
 for that PC to run Protel...
 That machine (Compaq evo) has 768 MB memory and is running W2k/sp3. All
 designs were in access format on the network CADserver.
 
 It is always possible, as well, that a particular installation has gotten
 trashed in some way, so reinstalling may be in order. Remember, when
 reinstalling Protel, to delete the *99SE* files in the System folder.
 (They aren't likely to be the problem here, but why not be thorough?)
 I did (after the first crash) re-install Protel using the description
 posted here several times but apparently that did not help.
 
 We thought it to be bad memory, too. That's the reason why the CEO took
 action and arranged new hardware overnight (usually that takes about 9
 months - coincidence?).
 I started from scratch with a brand new Sun Fire V60x (Xeon CPU, 2.8GHz)
 out of the box: a true virgin (... and a _very_ noisy beast too). Of course
 it is possible that this machine cointained a bad chip in it's 512 MB
 memory, but I would find that highly unlikelyEspecially with ECC memory
 If Sun keeps their delivery date I'll have an extra 2GB on monday; I will
 run memory tests monday night on both machines.
 
 I had to get the SCSI and ethernet drivers from the internet (that hardware
 is so new, W2k doesn't know it exists), installed W2k and was very pleased
 to see the built-in video card (turns out to be an ATI RAGE XL) accept a
 1600x1200 true color setting with the default driver so I did not load any
 other video drivers, just added W2kSP4.
 The network guys then added McAfee with automated updates from the server.
 I then installed Protel from the CD and added service pack 6; finally
 converted the Ddb's to filesystem format on the local HDD.
 Needless to say I rebooted between every single step of the whole process,
 just to be safe.
 But it still lets Protel crash after just one week of service... Thanks to
 the changed storage structure the damage is limited though.
 
 Where did I go wrong? Ok-ok, I'll see to it that I get another videocard.
 Any suggestions?
 No AGP slot in there,  just two PCI-X slots.
 
 As a comparison: at home I use a P2-910 in an Asus CUV4X motherboard with
 768MB (two brands) and a Nvidia RIVA TNT2/64 with 32MB on 1280x1024 (the
 monitor gets very fuzzy above that).
 The OS is W2K/sp4, virus scanner and firewall from Norman Security suite.
 I do not use a grounded outlet, have way too much software installed for a
 stable system, not re-installed Windows for over a year, use antique
 DOS-based utilities regularly and usually have 7 or more programs running
 simultaniously (in short: do everything one shouldn't do for stability's
 sake) and never had a Protel crash..Hey, I even do regular
 defragmentation on all drives.
 
 I think I'll take the CEO up on his remark 'why do you not work at home,
 then?'
 
 But seriously, folks: I'm stumped.
 If you guys are too: I don't blame you
 
 Leo
 

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Re: [PEDA] Vias do not tent when expected

2004-03-04 Thread Dennis Saputelli
hi Leo

i can't reproduce your problem, please see if i did it right

i set via default paramter to tent

i set a design rule to a big expansion to make it obvious
note: i used via specification in design rule to apply only
to the diameter and hole size of the defualt via type

i then placed some vias nad they were tented
on an individual vias i unchecked 'tenting'
and the big expansion showed up

this is all as expected

did i miss something ?

Dennis Saputelli


Leo Potjewijd wrote:
 
 At 03-03-2004 23:35, Ian Wilson wrote:
 On 12:28 AM 4/03/2004, Leo Potjewijd said:
 Hi.
 
 I just discovered something strange:
 
 I like my vias tented so I keep the tenting checkbox in the default via
 settings dialog checked.
 While interactively routing a PCB I noticed that the automatically placed
 vias did not get tented (and the forementioned checkbox is still checked)
 I do not want to end up with a board that has some vias tented and some
 not, and the global edit on the complete board afterwards is too easiliy
 forgotten.
 
 I'm sure I'm missing something obvious, but haven't a clue
 Please help me out, guys..
 
 
 There are two ways to force tenting on vias - or at least there are two
 places to control the solder mask expansion.  The via has a tenting
 attribute and there is a design rule that controls solder mask
 expansion.  I have no idea which has precedence, I would hope the tenting
 attribute of the via.  However you may want to check, and play with, the
 Manufacturing-Solder Mask expansion rule.  If you make the rule expansion
 ridiculously big do the auto-placed vias follow the silly expansion?
 
 I just did.
 They (the autoplaced vias) did, too Seems the rule takes precedence
 over the default setting.
 Only when the mfg rule specifically targets vias it has any effect, a rule
 specifying expansion for just surface and thru-hole pads does not change
 the expansion for the vias
 
 Before we had the tenting attribute you had to apply a large enough
 negative expansion to force tenting.
 
 The checkbox being tented but the actual via being untented does sound
 very odd - unless there is a conflict between the rules and the tent
 attribute.  Are the auto-placed vias the same dimensions as the manual
 placed vias?
 Yep.
   Are they both vias?
 Again, yep.
 
 The manual ones aren't free pads are they? (Just asking some possibly
 silly questions.)
 Hey, everyone stands the chance to overlook the obvious...
 
 What happens if you save as ASCII and then re-load?  What does the ASCII
 file show for a tented and untented via?  The ASCII records are not hard
 to read.
 AhemI would not say not hard to read, just not hard to understand..;)
 
 The ASCII file states a neat tenting=true for the tented vias; for the
 non-tented vias there is no such  statement. I would expect
 'tenting=false', but its completely missing
 
 Reloading the ASCII file does not solve the problem.
 Further probing reveals no solutions but yet another mystery: the via
 annular rings are calculated different from pad annular rings... I've seen
 this one before, but still have no clues.
 
 To top it all off: I'm running a fresh P99SE/sp6 installation on a brand
 new computer under a fresh installed W2kPro/sp4, all files on local disk.
 
 I just about had it with P99SE.
 
 Leo Potjewijd
 hardware designer
 Integrated Engineering B.V.
 
 [EMAIL PROTECTED]
 +31 20 4620700

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Re: [PEDA] Vias do not tent when expected

2004-03-04 Thread Dennis Saputelli

see my earlier response on this

the via chekcbox takes precedence
which i think is logical since you are at the most
specific level

only by having this ability can you easily make exceptions to the design
rule

without a NO DRC i for one would hate to wade through 
a DRC about this exception, but i see your point
that there may be stuff going on without one's specific
awareness

i always thought that soldermask expansion 
belonged better as a property of the pad or via than as a design rule
but at this point,  whatever

re the default primitive settings as in this example

there is one more point that may need clarification and which
may be at the root of the original post

the 'default' setting applied in Tool Prefs Defaults
ONLY applies when using the Place Via command

if instead you are manually routing a board
and the * key when changing layers
then the via in the Via routing style is used
and it does not carry the tenting attribute
even if it matches the size  hole of the default via

Dennis Saputelli


Abd ulRahman Lomax wrote:
 
 At 07:34 AM 3/4/2004, Leo Potjewijd wrote:
 
 I like my vias tented so I keep the tenting checkbox in the default via
 settings dialog checked.
 While interactively routing a PCB I noticed that the automatically
 placed vias did not get tented (and the forementioned checkbox is still
 checked)
 
 This discussion has gone back and forth a few times, yet some basic facts
 about the situation I found less than clear. There was an ambiguity about
 what was written. The aforementioned checkbox is the checkbox in the
 default via settings dialog. That is a setting which will control the
 configuration of vias manually placed while that setting is active. It does
 not affect vias that are already placed, nor will it necessarily affect
 what the autorouter places. (You might expect it to, but Protel is put
 together from various programs that do not always function together with
 complete rationality. The 99SE autorouter, in particular, is its own
 creature and I'm not surprised to find that it does not respect in any way
 the default settings, just as the default settings may be altered
 whenever you edit a primitive as it is being placed. The default settings
 dialog is a convenience of occasional use, not an absolute control.
 
 What I'm saying is that if the autorouter places vias which do not have the
 tenting checkbox checked, it is no big surprise once one is familiar with
 how 99SE works.
 
 Historically, tenting was controlled only by design rule, the tenting
 attribute was one of the latest things added in the Protel 99 release, as I
 recall. It's a convenience. It's not particularly one that we requested,
 since using design rules to control tenting was already quite sufficient.
 
 If there is a conflict between a design rule and the tenting checkbox, I'd
 place my bets on the design rule, given the history of the program. Which
 one is paramount? I don't know, and I'm not particularly motivated at the
 moment to go and test. I never check that tenting checkbox, precisely
 because I don't know the answer to the question. I do know that if the
 checkbox is unchecked and the design rule says tent, it will be tented.
 That's enough for me.
 
 Because the design rules are explicit and their scope can be readily
 determined (this gets even better in DXP), it is better design practice to
 control tenting through design rule than through a primitive attribute
 manually (or supposedly by default) assigned to each via. If somehow that
 checkbox got unchecked, how would you notice it?
 
 Suppose you have vias of a certain size and you want to tent some and not
 others? The checkbox does make a way for you to do this, but there is a
 better way, and that is to convert the vias to pads, give the pads a
 distinctive name (say TENTED for the ones you want tented), and create a
 pad-scope design rule for Free-TENTED.
 
 Vias are basically free pads with the restriction that they are only round
 and do not have names. If you want to distinguish some of these vias from
 others, it is better to select them and convert them to free pads (with
 Tools/Convert); then -- they will still be selected -- you can globally
 edit them to give them a distinguishing name.
 
 I do not want to end up with a board that has some vias tented and some
 not, and the global edit on the complete board afterwards is too easiliy
 forgotten.
 
 Yes. Precisely. That's why the design rule approach is better.
 
 They (the autoplaced vias) did, too Seems the rule takes precedence
 over the default setting.
 
 The basic error here is in assuming that the default settings. I can easily
 understand why one would make the assumption. *The default settings are a
 convenience to speed up manual design, they don't control anything.*
 
 What I don't know, it's an interesting question, is what happens if a
 design rule for tenting is in conflict with the checkbox on an individual
 via. I dislike ambiguities like

Re: [PEDA] Pads and single pin connectors.

2004-03-03 Thread Dennis Saputelli
maybe the pad of the E is not the same number as the pin of your
one pin

Dennis Saputelli


[EMAIL PROTECTED] wrote:
 
 Hey guys,
 
 I've got a problem I can't figure out.  We do a lot of interconnect with wires 
 soldered into a single pad.  We generally designate them as E?.
 
 I cannot figure out how to relate the pad to the schematic.  I've tried using the 
 one pin CON1 out of the library.  I've tried naming a port symbol.  Neither seem 
 to work with the Update schematic option.
 
 Any ideas on what I'm doing wrong?
 
 Michael Badillo
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Re: [PEDA] Vias do not tent when expected

2004-03-03 Thread Dennis Saputelli
in 99SE
the via tenting attribute (and/or the override)
will take precendence over a design rule expansion amount

as it should IMO

i have never seen one be untented mysteriously, but maybe i never
noticed it

Dennis Saputelli


Ian Wilson wrote:
 
 On 12:28 AM 4/03/2004, Leo Potjewijd said:
 Hi.
 
 I just discovered something strange:
 
 I like my vias tented so I keep the tenting checkbox in the default via
 settings dialog checked.
 While interactively routing a PCB I noticed that the automatically placed
 vias did not get tented (and the forementioned checkbox is still checked)
 I do not want to end up with a board that has some vias tented and some
 not, and the global edit on the complete board afterwards is too easiliy
 forgotten.
 
 I'm sure I'm missing something obvious, but haven't a clue
 Please help me out, guys..
 
 There are two ways to force tenting on vias - or at least there are two
 places to control the solder mask expansion.  The via has a tenting
 attribute and there is a design rule that controls solder mask
 expansion.  I have no idea which has precedence, I would hope the tenting
 attribute of the via.  However you may want to check, and play with, the
 Manufacturing-Solder Mask expansion rule.  If you make the rule expansion
 ridiculously big do the auto-placed vias follow the silly expansion?
 
 Before we had the tenting attribute you had to apply a large enough
 negative expansion to force tenting.
 
 The checkbox being tented but the actual via being untented does sound very
 odd - unless there is a conflict between the rules and the tent
 attribute.  Are the auto-placed vias the same dimensions as the manual
 placed vias?  Are they both vias?  The manual ones aren't free pads are
 they? (Just asking some possibly silly questions.)
 
 What happens if you save as ASCII and then re-load?  What does the ASCII
 file show for a tented and untented via?  The ASCII records are not hard to
 read.
 
 Not sure I have too many other ideas.
 
 Bye for now,
 Ian
 

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San Francisco, CA 94110 www.integratedcontrolsinc.com



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Re: [PEDA] How to highlight the Net in different colors in 99SE

2004-03-01 Thread Dennis Saputelli
that was the feature i was trying to suggest
i thought it was in there but i couldn't remember it exactly 
right either
thanks andy

Dennis Saputelli


Tony Karavidas wrote:
 
 Andy, that's brilliant! I don't think I ever knew about that feature!! That
 should fix him right up!
 
 I wonder how well it works in DXP with the masking???
 
  -Original Message-
  From: Andy Gulliver [mailto:[EMAIL PROTECTED]
  Sent: Monday, March 01, 2004 2:44 AM
  To: 'Protel EDA Forum'
  Subject: Re: [PEDA] How to highlight the Net in different
  colors in 99SE
 
  If you select Tools|Preferences then the Display tab, there's
  a checkbox for 'Use Net Color For Highlight'.
 
  To set the net colours, on the 'Browse PCB' tab select 'Nets'
  on the dropdown.  Scroll to the required net and click the
  Edit button.  This brings up a Net Properties dialog where
  you can set the net colour.
 
  Once this is done, select both nets and the tracks will be
  highlighted in their own colours.  Note that the highlight
  colour is the same for all layers, so not every 'near miss'
  will be genuine but it does help track them down.
 
  Regards,
 
  Andy Gulliver
 
   -Original Message-
   From: Tony Karavidas [mailto:[EMAIL PROTECTED]
   Sent: 28 February 2004 21:59
   To: 'Protel EDA Forum'
   Subject: Re: [PEDA] How to highlight the Net in different colors in
   99SE
  
  
   You can't because there is only one highlight color.
  
   If you had DXP you could filter by the two nets, such as
  (Net = 'A5')
   OR (Net = 'D0') and using the masking feature, these two nets are
   shows very clearly.
  
   Tony
  
-Original Message-
From: Adeel Malik [mailto:[EMAIL PROTECTED]
Sent: Saturday, February 28, 2004 5:44 AM
To: Protel EDA Forum
Subject: [PEDA] How to highlight the Net in different
  colors in 99SE
   
Hi All,
I have a populated board which has two nets
  shorted to each
other during assembly. I want to view both of the nets with
different colors in Protel 99SE PCB document, so that I
  can locate
the potential areas where the two nets are in close proximity.
   
Can some one tell me how to view the two nets with
  different colors
to solve the afore-mentioned problem in Protel 99SE ?
   
Thanks,
ADEEL MALIK
   
   
   
   
   
 
 
 
 

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Re: [PEDA] Placing Components on top of each other

2004-03-01 Thread Dennis Saputelli
most of us turn off component clearance check for a number of
good reasons, this among them

Dennis Saputelli


Trent Bates wrote:
 
 I am relatively new to Protel so this is probably an easy question for you
 guys.
 I am using Protel 99SE
 
 How do I place parts on top of one another?  For example I want to place a
 0805 resistor underneath a Radio module on the same side of the board.
 Physically there is space but in the Rules, the Component Distance
 Constraint will not let me.  I know that Multilayer Check will allow me to
 place a surface mount part underneath a through hole part if it is on the
 other side of the board but I want it on the same side of the board.  I know
 the answer is obvious but I can't find it.
 
 Trent Bates

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Re: [PEDA] How to highlight the Net in different colors in 99SE

2004-02-28 Thread Dennis Saputelli
but you can make the nets different colors
you just can't change the highlight color
which i think is what he wanted
just double click the net in browse PCB

Dennis Saputelli

Tony Karavidas wrote:
 
 You can't because there is only one highlight color.
 
 If you had DXP you could filter by the two nets, such as (Net = 'A5') OR
 (Net = 'D0') and using the masking feature, these two nets are shows very
 clearly.
 
 Tony
 
  -Original Message-
  From: Adeel Malik [mailto:[EMAIL PROTECTED]
  Sent: Saturday, February 28, 2004 5:44 AM
  To: Protel EDA Forum
  Subject: [PEDA] How to highlight the Net in different colors in 99SE
 
  Hi All,
  I have a populated board which has two nets shorted
  to each other during assembly. I want to view both of the
  nets with different colors in Protel 99SE PCB document, so
  that I can locate the potential areas where the two nets are
  in close proximity.
 
  Can some one tell me how to view the two nets with different
  colors to solve the afore-mentioned problem in Protel 99SE ?
 
  Thanks,
  ADEEL MALIK
 
 
 
 
 

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Re: [PEDA] Protel - server problems

2004-02-05 Thread Dennis Saputelli
norton antivirus ?

ds


Dom Bragge wrote:
 
 I'm having a few probs with my setup here  just wanted to bounce the
 symptoms off you for any suggestions I could follow up on.
 
 I am running 99SEsp6  XP  am connected to a network.
 
 History:
 I had My Documents mapped to the H: drive (on a server) instead of my
 local machine for safety sake ( making backups simple). The problem
 with that is there is often some sort of lag when I save a (say 3meg)
 Protel database. Instead of taking 1sec, like when I save on my local
 disk, it *sometimes* takes nearly 60seconds onto the H drive. Sometimes
 it has been almost instantaneous. This doesn't seem to be related to
 network traffic, more like waiting for something to timeout, as I can
 send a 10meg file to  from the same H drive  it does that smartly.
 
 I only have delay probs with Protel saving  no other program.
 
 Can anyone give a hint of what might be happening here? Have you seen
 anything like this?
 
 --
 Regards,
 
 Dom
 
 Dom Bragge, CID MIEEE  | Silverbrook Research PL, PO Box 207
 Snr PCB Layout Engr| Balmain NSW 2041, AUSTRALIA
 Ph +61-2-9818-6633xt163| [EMAIL PROTECTED]
 
 This message is sent using PostCast Server Professional Trial:
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Re: [PEDA] Protel - server problems

2004-02-05 Thread Dennis Saputelli
we don't have problems with the DDB over the network
nor w/ compact on close except for the small time it
takes to do the compact which is maybe roughly
10 secs on a 10M file

Dennis Saputelli


May Scott wrote:
 
 Are you using the DDB database format - if I remember rightly, it's an
 access database, which according to our network support guys are just
 tragic over networks...
 
 You mention it's when you save - have you selected the Compact database
 on save option?  I know that function can be slow even on local drives
 at times...
 
 Thanks,
 Scott.
 __
   Scott May
 
 -Original Message-
 From: Dom Bragge [mailto:[EMAIL PROTECTED]
 Sent: Thursday, 5 February 2004 11:04 AM
 To: protel
 Subject: [PEDA] Protel - server problems
 
 I'm having a few probs with my setup here  just wanted to bounce the
 symptoms off you for any suggestions I could follow up on.
 
 I am running 99SEsp6  XP  am connected to a network.
 
 History:
 I had My Documents mapped to the H: drive (on a server) instead of my
 local machine for safety sake ( making backups simple). The problem
 with that is there is often some sort of lag when I save a (say 3meg)
 Protel database. Instead of taking 1sec, like when I save on my local
 disk, it *sometimes* takes nearly 60seconds onto the H drive. Sometimes
 it has been almost instantaneous. This doesn't seem to be related to
 network traffic, more like waiting for something to timeout, as I can
 send a 10meg file to  from the same H drive  it does that smartly.
 
 I only have delay probs with Protel saving  no other program.
 
 Can anyone give a hint of what might be happening here? Have you seen
 anything like this?
 
 --
 Regards,
 
 Dom
 
 Dom Bragge, CID MIEEE  | Silverbrook Research PL, PO Box 207
 Snr PCB Layout Engr| Balmain NSW 2041, AUSTRALIA
 Ph +61-2-9818-6633xt163| [EMAIL PROTECTED]
 
 This message is sent using PostCast Server Professional Trial:
 http://www.postcastserver.com/
 
 
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Re: [PEDA] TO-220 4th pin?

2004-01-29 Thread Dennis Saputelli

re 99SE

we use the 4th pin approach, then you don't have this issue
with the DRC (losing the manual net assignmnet)

on DB conns we have 27 pins for a DB25 etc

on BNCs we have 4 pins (3 gnds)
we stack up the gnd pins in the schm lib
and hide the pin numbers for 2 of them
this makes the schematics prettier

when you wire to the stacked up pins
you get an autojunction which is the tip off as
to what is going on

never had any problem with this approachs

Dennis Saputelli



Tony Karavidas wrote:
 
 I do that all the time. The hole for the TO-220 tab is the hole that will be
 in the board. You don't need to place another 'free' hole. My lay-flat
 TO-220 pad is defined as pad number 0 and is 0.125 so I can use a machine
 screw and nut to hold it down.
 The area below it is part of my GND polygon pour. I manually connect this
 PAD0 to the GND net. To expose the copper, I place a fill on the Top Solder
 mask layer and it's usually the size of the tab and the body (helps if the
 back of the body is metal and not plastic)
 
 This will DRC properly because of the manual net assignment, however the
 thing to watch is when you do an UpdatePCB from the schematic. It will try
 and generate a macro to remove U?_PAD0 from net GND. Just delete that macro
 and continue.
 
  -Original Message-
  From: Dom Bragge [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, January 28, 2004 9:23 PM
  To: protel
  Subject: [PEDA] TO-220 4th pin?
 
  I just would like to ask a question about how you handle
  TO-220 footprints ( the like)...
 
  I have the three (electrical) pin device, that's fine.
  I'm placing the T)-220's flat on the board.
 
  What if I want to (selectively) put copper on the top layer
  under the TO-220  have a suitable soldermask antipad? This
  could aid in cooling without resorting to an actual heatsink.
  How should I best do that?
 
  Do I place on the board a free pad, rectangle, with a hole
  the same size as the hole for the TO-220 tab? Seems a bit
  ugly, two holes etc etc but it should probably give me the
  SMask opening.
 
  Do I make a 4pin lib part, have a 4th pin on the footprint
  being the large hole  add a polygon connected to that net? I
  suppose I'll have to add an opening for the SMask on the
  TO-220 footprint as well.
 
 
  What say you?
 
  --
  Regards,
 
  Dom   99SESP6
 
  Dom Bragge, CID MIEEE  | Silverbrook Research PL, PO Box 207
  Snr PCB Layout Engr| Balmain NSW 2041, AUSTRALIA
  Ph +61-2-9818-6633xt163| [EMAIL PROTECTED]
 
 
 
 
 

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Re: [PEDA] Leaving Protel

2004-01-28 Thread Dennis Saputelli
why don't you keep us posted once in a while about how 
you like it, ups  downs vs. protel etc.
see ya

Dennis Saputelli


Tim Fifield wrote:
 
 Hi All,
 
 This is my last week with this company, and I'm going to be learning OrCad
 starting Monday at my new job.
 
 I just wanted to take a minute to thank everybody on this forum who has
 helped me over the past 3 years with Protel. It's been a great learning
 experience!
 
 Thanks again!
 
   gains in quality come from meticulous attention to detail and every step
 in the manufacturing process must be done as carefully as possible, not as
 quickly as possible
 
 -David Packard
 
 Tim Fifield, CET
 International Rectifier - Automotive
 
 PS. If anybody knows of any similar forums or websites for OrCad please let
 me know.
 

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Re: [PEDA] Antwort: Autorouter

2004-01-28 Thread Dennis Saputelli
so does the Electra router do fan outs that are nice so that you
don't have to do them manually?

Dennis Saputelli


Mike Reagan wrote:
 
 Emanuel,
 I forgot to mention you can also use the layer assignment in classes.  This
 also works well.  I have found this be hard to set in Spectra.
 
 Mike Reagan
 
 -Original Message-
 From: Emanuel Zimmermann [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, January 21, 2004 11:03 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Antwort: Antwort: Autorouter
 
 Mike
 
 Thanks for this detailed answer. It seems that I have to try the classes
 trick to get design rules easier to specctra. I was not aware of this -
 currently we work with manually edited .rul files.
 
 Emanuel
 
 ---
 MPL AG   www.mpl.ch
 Emanuel Zimmermann   [EMAIL PROTECTED]
 Manager RD   Phone: +41 56 483'34'34
 Taefernstrasse 20   Fax:  +41 56 493'30'20
 
 CH-5405 Daettwil
 ---
 
 edsi [EMAIL PROTECTED] schrieb am 21.01.2004 14:16:46:
 
  Emanuel
  We also suspect Protel is at fault for the 28 mil holes.  I think it
  is a default in Protel setup.
  As far as High Speed design rules,  You will need to stick with
  spectra for now, since Electra does not support differential pairs
  of matched lengths.  I did not try blind and buried vias, but I did
  use prerouted via in pad.  Electra was cleaner since it let these
  connections alone and I did not have to create any forget commands.
  We also tested the BUS command on both routers. The test board was
  a simple backplane with identical connectors on same Grid. Spectra
  was slightly better however,  neither Electra or Spectra routing
  would be acceptable with this command.
  One thing we did noticesince both routers use a manhattan
  topology to place traces,  On large busses, Electra has  very few
  loops.  It sticks to the floorplan very well.  I have a tendency to
  use the limit way command on most of my designs.  This forces the
  router to lay traces parrallel to each other on the same layer. This
  increases the density of the routing.  Limit way is a little tighter
  on Spectra.  I ran tests on both routers, using limit way then ran
  test without limit way.  In both cases, Electra managed 500-700 less
  vias out of 7800.
 
  What I was most impressed with was that it left the locked preroutes
  tollally alone. Honestly, this is the first router that this worked
  with.   If  you think Spectra is leaving them alone, look closly at
  your design.  On some occasions it place traces either over or
  around your preroutes.  The only way to avoid this is to create
  forget classes.
 
  Here is the way the classes and DSN file works in Protel.   Protel
  does not export classes. I wish it would.  If you want to create
  widths lets say for DATA D0-D7, created a classs called DAT0_7, then
  create and invidual width rule for that class.  When Protel exports
  the DSN file , it will assign an INDIVIDUAL rule to the nets in the
  class.  The same applies to via  type, toplogy, max via, and
  clearance. Protel extracts the class and breaks it down to net.
  That is perfectly fine ...perhaps cumbersome but it works.  You
  still may want to look at this router.  ELecta is working on adding
  High Speed rules
 
 
  Mike Reagan
  EDSI
  Frederick MD
 
 

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Re: [PEDA] Autorouter

2004-01-21 Thread Dennis Saputelli
what you say is true (good products ruined)
but it is too late

in other words this is the M.O. of biz today
so wishing it were otherwise makes no difference

when you consider:
1] more than a year has passed since Situs was released
2] it is 'still under developement' by their own recent words
3] they have never produced a usuable router *of their own making*

i stand by my idle wish

BTW - re #3
i find the 99SE router (which is a direct descendant of 
Neruoroute which they had purchased)
to be usuable for many needs ranging from simple to moderate
it is certainly not very SMD aware and is certainly not up to
today's technology, but how could it be? it's old

remember TRAXSTAR ?  heh heh
that was an in house router by protel a million years ago
i still have the dongle
it never did anything useful and wasn't real cheap by those day's 
standards

during the 2.8 windows era their router wasn't worth anything either
they didn't even claim it was
the router of choice at that time was from Masstek
can't recall the name right now
i still have the dongles

so i hope this shows the reasoning behind my thinking on this 
matter

Dennis Saputelli


Bagotronix Tech Support wrote:
 
  if it is what it seems to be i will repeat that i think that altium
  should just buy them and integrate it
  after all that was neuroute's biz strategy
 
 Be careful what you wish for - you might get it.
 
 Seriously, when a firm with a great product gets bought by another firm, it
 usually has detrimental results on the product that made the former great.
 I think I can count on one hand the number of real world examples of where a
 buyout actually improved the product or service.  The business landscape is
 littered with the remains of once good products and companies that were
 ruined by a buyout.
 
 Best regards,
 Ivan Baggett
 Bagotronix Inc.
 website:  www.bagotronix.com
 
 - Original Message -
 From: Dennis Saputelli [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Tuesday, January 20, 2004 8:45 PM
 Subject: Re: [PEDA] Autorouter
 
  no joke
  i know it is a tall order (big wish)
  but why route a big board all 4/4 (or 5/5) when only a little area needs
  it?
 
  i guess you would just define a rectangle and then outside that it would
  shift gears
 
  BTW my idle wish aside,
  mike seems quite excited by this router and he knows this business well
 
  if it is what it seems to be i will repeat that i think that altium
  should just buy them and integrate it
  after all that was neuroute's biz strategy
 
  Dennis Saputelli
 
 
  Igor Gmitrovic wrote:
  
   And add 6/6 in between to smooth the transition.
  
   Are you sure you are joking here? :)
  
   Igor
  
   -Original Message-
   From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
   Sent: Wednesday, 21 January 2004 11:48 AM
   To: Protel EDA Forum
   Subject: Re: [PEDA] Autorouter
  
   $3K for the full version seems quite reasonable if it will do what
   spectra does
  
   now we just need a router that will do 4/4 around BGAs and then
   switch to 5/5 or 8/8 outside that region!  -:)
  
   ds
  
   edsi wrote:
   
Joe and Dennis,
This company has no affiliation with Altium.  Yes I agree ELECTRA is
 the routing solution for all of Altium's products.
Dennis, it will do BGAs, it will do it all. When importing back from
 the router, it exhibits the same chararteristics as Spectra. Every via is
 converted to 28 mils.  Double hits are common on Vias, but this is a minor
 problem compared to the quality of routing.  The full version will set you
 back another 3K.  I probably can save that if I can buy PCB ala carte from
 Protel since I have no use for their other add ons.
   
Mike Reagan
EDSI
Frederick MD
   
-- Original Message --
From: Dennis Saputelli [EMAIL PROTECTED]
Reply-To: Protel EDA Forum [EMAIL PROTECTED]
Date:  Tue, 20 Jan 2004 11:28:34 -0800
   
what does it cost ?
how does it like BGAs?

does it still convert all the via holes to 28 or is that a protel
 bug?

maybe altium should give up and just buy the ELECTRA company ?

ds


edsi wrote:

 Hello All,

  
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   San Francisco, CA 94110 www.integratedcontrolsinc.com
  
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Re: [PEDA] Autorouter

2004-01-20 Thread Dennis Saputelli
what does it cost ?
how does it like BGAs?

does it still convert all the via holes to 28 or is that a protel bug?

maybe altium should give up and just buy the ELECTRA company ?

ds


edsi wrote:
 
 Hello All,
 
 I wish to share my excitement on new autorouter for Protel.  The router is from 
 konekt.com, named ELECTRA.  Electra is available in several configurations, but I 
 wish to share that I spent a considerable amount of time baselining this software. 
 The router accepts DSN files, and is very similar in operation to Spectra less a few 
 high speed commands.
 As far as routing speed,  it is slightly slower than Spectra, but the accuracy of 
 the traces are cleaner. On three separate tests of the same design, Electra was 
 consistent with 500- 600 less vias.  It was also consistent on all of my track 
 lengths. The test board had 1984 components, so this was not a trivial routing test.
 The router also observed my protected traces.  I can not speak highly enough of this 
 product, and no I do not have a vested interest in it
 Download their demo.  I highly recommend it
 
 Mike Reagan
 EDSI
 Frederick MD
 

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com


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Re: [PEDA] Autorouter

2004-01-20 Thread Dennis Saputelli
$3K for the full version seems quite reasonable if it will do what
spectra does

now we just need a router that will do 4/4 around BGAs and then
switch to 5/5 or 8/8 outside that region!  -:)

ds


edsi wrote:
 
 Joe and Dennis,
 This company has no affiliation with Altium.  Yes I agree ELECTRA is the routing 
 solution for all of Altium's products.
 Dennis, it will do BGAs, it will do it all. When importing back from the router, it 
 exhibits the same chararteristics as Spectra. Every via is converted to 28 mils.  
 Double hits are common on Vias, but this is a minor problem compared to the quality 
 of routing.  The full version will set you back another 3K.  I probably can save 
 that if I can buy PCB ala carte from Protel since I have no use for their other add 
 ons.
 
 Mike Reagan
 EDSI
 Frederick MD
 
 -- Original Message --
 From: Dennis Saputelli [EMAIL PROTECTED]
 Reply-To: Protel EDA Forum [EMAIL PROTECTED]
 Date:  Tue, 20 Jan 2004 11:28:34 -0800
 
 what does it cost ?
 how does it like BGAs?
 
 does it still convert all the via holes to 28 or is that a protel bug?
 
 maybe altium should give up and just buy the ELECTRA company ?
 
 ds
 
 
 edsi wrote:
 
  Hello All,
 

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com


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Re: [PEDA] Autorouter

2004-01-20 Thread Dennis Saputelli
no joke
i know it is a tall order (big wish)
but why route a big board all 4/4 (or 5/5) when only a little area needs
it?

i guess you would just define a rectangle and then outside that it would
shift gears

BTW my idle wish aside,
mike seems quite excited by this router and he knows this business well

if it is what it seems to be i will repeat that i think that altium
should just buy them and integrate it
after all that was neuroute's biz strategy

Dennis Saputelli


Igor Gmitrovic wrote:
 
 And add 6/6 in between to smooth the transition.
 
 Are you sure you are joking here? :)
 
 Igor
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, 21 January 2004 11:48 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Autorouter
 
 $3K for the full version seems quite reasonable if it will do what
 spectra does
 
 now we just need a router that will do 4/4 around BGAs and then
 switch to 5/5 or 8/8 outside that region!  -:)
 
 ds
 
 edsi wrote:
 
  Joe and Dennis,
  This company has no affiliation with Altium.  Yes I agree ELECTRA is the routing 
  solution for all of Altium's products.
  Dennis, it will do BGAs, it will do it all. When importing back from the router, 
  it exhibits the same chararteristics as Spectra. Every via is converted to 28 
  mils.  Double hits are common on Vias, but this is a minor problem compared to the 
  quality of routing.  The full version will set you back another 3K.  I probably 
  can save that if I can buy PCB ala carte from Protel since I have no use for their 
  other add ons.
 
  Mike Reagan
  EDSI
  Frederick MD
 
  -- Original Message --
  From: Dennis Saputelli [EMAIL PROTECTED]
  Reply-To: Protel EDA Forum [EMAIL PROTECTED]
  Date:  Tue, 20 Jan 2004 11:28:34 -0800
 
  what does it cost ?
  how does it like BGAs?
  
  does it still convert all the via holes to 28 or is that a protel bug?
  
  maybe altium should give up and just buy the ELECTRA company ?
  
  ds
  
  
  edsi wrote:
  
   Hello All,
  
 
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 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com
 
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 visit http://www.mci.com
 

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Re: [PEDA] Autorouter

2004-01-20 Thread Dennis Saputelli
4 mil line / 4 mil space

below 5/5 price and flakiness go up

Dennis Saputelli


Thomas wrote:
 
 Please excuse my ignorance, what are 4/4, 5/5 etc...?
 
  -Original Message-
  From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, 21 January 2004 12:25
  To: Protel EDA Forum
  Subject: Re: [PEDA] Autorouter
 
 
  And add 6/6 in between to smooth the transition.
 
  Are you sure you are joking here? :)
 
  Igor
 

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Re: [PEDA] P99SE ONLINE DRC stopped working help!

2004-01-09 Thread Dennis Saputelli
help!
this might be something REALLY stupid but i am banging my head ...

anyone know why ONLINE DRC might have stopped working for me?
here is punchlist
99SE
online drc checkbox IS on
drc 'layer' is on
various rules are set up 'normally' and enabled
obstacle is 'avoid'

as i manually route with PT i can draw right through all the wrong
pads at all the wrong clearances

if i run the batch DRC it correctly shows the errors and lights 
them up bright green

it's just that during manual routing the online 
DRC is not working anymore

BTW, if i turn push obstacle on that works, but if i turn it back
to avoid obstacle it does NOT avoid

if i change a rule and push CLOSE the online DRC does not run 
as it usually does

something has changed radically here

-- stop --- poke around some more, reboot etc

same prob

i opened another DDB, no probs
the online DRC works! (first DDB still open)

now i am getting worried about my data

other boards in same original DDB, same problem, no online drc

i made a new fresh DDB and copied the pcb file into it, no go, same prob

i deleted all rules, no help


Dennis Saputelli


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Re: [PEDA] P99SE ONLINE DRC stopped working help!

2004-01-09 Thread Dennis Saputelli
well to respond to myself  somewhat embarassededly
(it was late and i thought i was missing something stupid)

i didn't look at the ONLINE 'TAB' 

'problem' solved

ds


Dennis Saputelli wrote:
 
 help!
 this might be something REALLY stupid but i am banging my head ...
 
 anyone know why ONLINE DRC might have stopped working for me?
 here is punchlist
 99SE
 online drc checkbox IS on
 drc 'layer' is on
 various rules are set up 'normally' and enabled
 obstacle is 'avoid'
 
 as i manually route with PT i can draw right through all the wrong
 pads at all the wrong clearances
 
 if i run the batch DRC it correctly shows the errors and lights
 them up bright green
 
 it's just that during manual routing the online
 DRC is not working anymore
 
 BTW, if i turn push obstacle on that works, but if i turn it back
 to avoid obstacle it does NOT avoid
 
 if i change a rule and push CLOSE the online DRC does not run
 as it usually does
 
 something has changed radically here
 
 -- stop --- poke around some more, reboot etc
 
 same prob
 
 i opened another DDB, no probs
 the online DRC works! (first DDB still open)
 
 now i am getting worried about my data
 
 other boards in same original DDB, same problem, no online drc
 
 i made a new fresh DDB and copied the pcb file into it, no go, same prob
 
 i deleted all rules, no help
 
 Dennis Saputelli
 
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 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com

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Re: [PEDA] Protel 99SE Explorer file type icons disappearing

2004-01-09 Thread Dennis Saputelli
i wonder if the icons are handled by windows
i certainly see flaky icon behavior by windows

re repair
i have never had it do anything useful (or harmful) for me

Dennis Saputelli


Jeff Adolphs wrote:
 
 Have you ever had the Protel 99SE Explorer file type icons disappear? I have tried a 
 fresh install of the software and using DDB repair and still the file type icons 
 disappear. Is this normal? I find it disconcerting and when it happens I wonder if 
 the Database needs repaired. BTW how do you know when a Database needs repaired?
 
 Jeff Adolphs
 Westerville, OH
 

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Re: [PEDA] P99SE ONLINE DRC stopped working help!

2004-01-09 Thread Dennis Saputelli
you're right that restarting protel often fixes things

sometimes it even takes a cold boot, but not too often

on another topic
anyone notice that Norton AV has gotten VERY cranky just lately ?
(result of recent live updates i assume)

we just had a serious of serious constant blue screen deaths
everything *was* be running perfectly previously

was solved by completely removing NAV (no simple matter)
and putting on the corp edition

removing NAV by using the add/remove in no way completely removes it
i had to get an outsider to come in and spend some time with a 
utility and then manually deleting tons of registry keys before
the corp edition would install properly

Dennis Saputelli


Steve Wiseman wrote:
 
 09/01/2004 21:28:32, Abd ul-Rahman Lomax
 [EMAIL PROTECTED] wrote:
 
 However, the fact that another ddb has DRC working pretty
 much rules out a
 program glitch.
 
 Hmm - I still find that stopping  restarting Protel often fixes
 things when all other approaches have failed and I'm thinking this
 makes absolutely no sense.  This may be one of those times...
 
 Steve
 

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Re: [PEDA] BGA Tenting/Specifications

2004-01-05 Thread Dennis Saputelli
re SE99
we tent them 
you want to do this to improve yield

then place free pads on bottom side soldermask to allow probing

generally i think plugging is to be avoided for various reasons
(assuming by 'plugging' we are referring to put some material in the 
hole)

in DXP you can make top and bottom solder masks different from each 
other

Dennis Saputelli



Michael Biggs wrote:
 
 Can get I a few opinions about how you guys handle BGA components in your
 layouts?
 Do you generally tent (using tenting in Protel99SE via properties) the
 dog-bone vias that branch off of each BGA pad to prevent solder thieving or
 specify in your specifications to Plug top side vias. There may be other
 ideas and I'm sure the responses will vary on the assembly methods.
 Generally I see a reflow then wave on these mixed technology PWA I am
 prototyping.
 Thanks in advance.
 -MB

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Re: [PEDA] Protel 99SE ERC

2003-12-21 Thread Dennis Saputelli
i don't think 99SE ERC will catch this

i did look into it at that time, i will look again later

Dennis Saputelli


Abd ul-Rahman Lomax wrote:
 
 At 09:42 PM 12/19/2003, Dennis Saputelli wrote:
 i once had a power port symbol +12V2 connected to one end of
 a resistor
 
 the rest of the board was all +12V for that power and i didn't
 notice it
 good 'ol cut and paste - it wasn't my fault! :)
 
 anyway the resistor didn't go anywhere on one end
 and in the usual mad proto rush it was shipped because the
 DRC was happy
 
 DRC would be happy, but a properly configured ERC would not. I always have
 ERC report unconnected pins, and I nail them all down: if there is a
 deliberately unconnected pin, I place a No-ERC directive on it, which from
 then on suppresses the ERC report.
 
 does DXP catch this ?
 
 Since 99SE would, I assume DXP also would.
 
 BTW, this is not a 'single pin net' since the netlist shows 2
 items:
 +12V2
 R112-2
 
 the 'isolated' power port counts kind of like a 'pin'
 
 No, I don't think so, unless ERC is misconfigured. Normally, writing here,
 I'd check this, but time is short today. But even if ERC will detect such
 single pin nets, there is still a problem; what if there had been, say, a
 capacitor also connected to +12V2? DXP is not, I am sure, going to catch
 this. But there are procedures that could use 99SE/DXP tools to make it
 easy to find such problems. But you still have to remember to look for them.
 
 i poked around a bit in 99SE and couldn't find a way to flag it
 
 yes manually inspecting the netlist would have caught it and
 truthfully isn't very hard to scan through even a big net list
 for this sort of thing
 
 I used to always run an NC pin list from PCB, it was part of the Tango DRC
 options. A resistor appearing in that list would be a big red flag. It can
 be a very good idea to look at a list of nets (not a full net list but a
 list of net names) to see if there are any oddities, like
 
 DATA1
 DATAl
 
 (Yes, those are different! If they weren't, they wouldn't show up as two
 entries in the list, would they? A really sophisticated ERC/DRC would
 generate a warning if there were such similar net names)
 
 and for the record ...
 at one time i may have been in the DXP-basher camp (some time ago)
 
 at this point since i have not used DXP much i don't think it would
 be objective or fair for me to bash
 i hope i have not lately presented such an attitude
 
 i would prefer to be categorized as simply a non-DXP user who is
 very reluctant to 'move on' based on what i saw during a few
 brief forays
 
 when 2004 ships i intend to give it another go
 
 Since I'm exploring DXP now, I'm thinking of writing a 99SE - DXP training
 document, that focuses on informing an experienced 99SE user how to move to
 DXP

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Re: [PEDA] Power supply pins

2003-12-20 Thread Dennis Saputelli
are you referring to DXP ?

i don't see this prob in 99SE

the topic of power pins being hidden or not and separate parts for
containing power pins only has been hashed over quite a bit here

my 2 cents FWIW 
keep the power pins right on logic BLOCK type symbols
with the rest of the pins

these days with so many different core voltages and possibly
separate isolated voltages of the same magnitude it's just plain
easier to control and see what is going on
rather than having to hunt around for a separate section and
then match up the designator, etc.
as to clutter it hardly matters to me since these chips are becoming
porcupines anyway

the messy exception i make to the above statement is for op amps
and maybe something like a QUAD NAND package which from this perspective
is about like an op amp

it's just so annoying to have the power pins jump around and have to
clear the
space, exp. for the byp caps
i think in this case the argument for a power section (aka 'part') makes
sense

BTW
in my practice i am finding that producing a nice looking
and pretty schematic to be less and less important
i.e., once the whole thing is debugged and in production
i seem to have ever decreasing need to look at the schematic

things are so fast moving that the bd is obsolete or junk 
before you need to fix it (or so reliable it never comes up)

if it doesn't work on test get another assembler or
fix the process, there just isn't enough time or margin 
to debug  troubleshoot at the schematic level

remember when they used to repair carburetors?
now they just bolt a new one on

likewise i seem to be seeing less and less published 
schematics which would remove another reason for making
a pretty schematic

obviously others will have different needs and perspectives 
and i would like to make perfect looking and clear schematic as
much as the next designer but sometimes a bag of net 
labels is enough to get the job done

Dennis Saputelli


Laurie Biddulph wrote:
 
 Hello and thank you for your extensive response.
 I do apologise for not getting back to you earlier but have been fairly busy.
 I think it is generally good practise to always have EVERY pin exposed even power 
 supply pins but I do feel that putting the power pins off to one side is a neater 
 way than having as part of a main component symbol. The only problem I have found so 
 far, and I can't explain why, is that putting the power parts on to a separate page 
 resulted in Protel wanting to add a complete extra chip to the pcb when I did an 
 update.
 
 I will study your other comments but am often amazed at how much extra work one has 
 to do sometimes to achieve a basic feature - not bad for ASU$9000!
 
 Best Regards
 Laurie Biddulph
 http://www.elby-designs.com
   - Original Message -
   From: Abd ul-Rahman Lomax
   To: Protel EDA Forum
   Sent: Friday, December 12, 2003 5:07 AM
   Subject: Re: [PEDA] Power supply pins
 
   {this message bounced first time, outgoing mail server couldn't find
   techservinc.com)
 
   At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
   I hate having power supply pins as part of schematic component symbols
   (especially opamps and logic gate chips). I prefer to create an additional
   `component part' in the chip purely for the power supply pins. This makes
   it easier to assign decoupling components to the chip as well as reduce
   clutter in the main part of the schematic.
 
   This is a very legitimate way of dealing with the problem, as is having the
   power pins be part of the symbol. Hidden pins have restricted application,
   some say that they should never be used, but that goes too far. If you have
   a digital design with standard logic, hiding the power pins may be acceptable.
 
   However, if a technician is going to have any difficulty later figuring out
   which pin on a part is, for example, ground, it is better to be explicit.
 
   Making symbols with power pins as a separate part of the symbol, while it
   is a little more complex -- in creating the symbols -- is really the best
   of both worlds. All the power parts can be placed on a page -- or part of a
   schematic page -- which shows power nets and bypass cap allocations. This
   leaves the rest of the schematic for signal flow and logic, and not having
   to deal with power connections and bypass on those pages saves both time
   and space, and results in a schematic that is easier to read. The only
   negative I can think of is that in a split-supply design the power
   assignments are not necessarily on the same page so an error in assignment
   might be less obvious.
 
   I consider the improvement in general readability to outweight that; it
   just requires a little more caution, since, so far, there is no ERC for this.
 
   (If component classes could be set up in schematic and assigned power
   supply classes, ERC would be possible, where a component was assigned the
   incorrect power supply, i.e., an analog part gets a digital supply

Re: [PEDA] What could we expect in next Altium EDA tools?

2003-12-19 Thread Dennis Saputelli

So Hamid, are you going to give Protel 2004 a spin 
when it is released?

it appears that the PCB side will essentially be DXP SP3

and as Ivan has asked have you identified a competitive alternative 
for you and your customers?

we have 2 seats here and also have yet to embrace DXP 

but at some point i guess we will need to either jump ship or
bite the bullet (hey! 2 cliches in one sentence)

the years of work in the libraries form a sort of trap, i 
wouldn't relish having to recreate all those parts

TIA for any info

Dennis Saputelli


Hamid A. Wasti wrote:
 
 Bagotronix Tech Support wrote:
 
 What did you tell them to
 buy instead of DXP?  Could they still buy 99SE, or did you recommend some
 other brand?
 
 When we do large product development projects for our clients, we
 deliver the board files only in Protel format.  If the client wants to
 make changes in house with our support, they need to purchase Protel and
 we make a commitment to teach  support them.  Over the years we have
 been directly responsible for the sale of several seats this way and
 indirect responsible for the sale of several more because after
 acquiring in-house expertise, the company decided to increase the number
 of seats.
 
 As for the canceled sales, we struck a deal with one client for them to
 teach us their CAD system.  In another case, the client is still trying
 to decide what CAD system to get, as we have made it clear that we will
 not be supporting DXP and understandably they do not want to buy a dead
 end product like 99SE
 
  I don't mean to sound negative, but these issues are important, and I'm not
  going to get excited over Nexar and LiveDesign until I see answers to these
  questions.
 
 Those issues are indeed important, but there is a more fundamental
 issue:  Will the product actually work, or will it be a waste of your
 time and money?  Considering Altium's recent history, you would be lucky
 if you get the point of actually having to realistically worry about the
 issues you mentioned in your post.
 
 Hamid
 

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Re: [PEDA] Solder mask...

2003-12-19 Thread Dennis Saputelli
my experience is the same as John's on this issue
i.e. do open it up

we once shipped a board to fab and forgot to do this
they called us up and advised that we do and used a descriptive 
term (opening up the mask) which i can't recollect

it wasn't 'block' but i can't recall it, something like 
'moat' or 'bar'?

any one know the common term ?

Dennis Saputelli



John A. Ross [RSDTV] wrote:
 
  -Original Message-
  From: Tom Robinson [mailto:[EMAIL PROTECTED]
  Sent: Tuesday, December 16, 2003 9:26 PM
  To: Protel EDA Forum
  Subject: [PEDA] Solder mask...
 
 
  Is it ok to block open the solder mask on gull-wing i.c.'s with .4mm
  AND .5mm pitches?
 
  It seems to get enough web in between the pads to stick will cause a
  LPI registration thats too tight, with possible smearing. And if you
  make the pads themselves too narrow -- thats another problem.
 
 Tom
 
 I always block open the pads on these pitches.
 
 It is not so easy to get a manufacturer to get SM registration right at
 these tolerances although it is possible.
 
 Most quick turn boards I have had to take as 'free issue' parts to assemble,
 which have not blocked off these areas, I have had quality issues with the
 finished joints around these fine pitch pads.
 
 I have never had an issue with blocking them open, biggest solder mask issue
 I have ever had was when the SM thickness to finished pad height
 differential was too much (SM height was bigger than finished pad by a lot)
 and we had gasketing issues from the paste screen to the pad, causing
 problems like, paste bleeding out on the PCB side of the screen, some
 shorts, failed 3d inspection after print cycle, loose solder ball symptoms
 and aperture blockages, with our MPM printer having to make undue clean
 cycles between prints. Also undue print down force had to be applied to
 squeegee blades, increasing wear and decreasing accuracy.
 
 Never had solder ball or short issues as long as the board is printed
 correctly and the oven specifically profiled to suit your board. (also
 optimise paste volumee, height, reductions...)
 
 John

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2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com


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Re: [PEDA] Protel 99SE ERC

2003-12-19 Thread Dennis Saputelli
ok, point taken, thanks for the encouragement, keep 'em coming

how about this one:

i once had a power port symbol +12V2 connected to one end of 
a resistor

the rest of the board was all +12V for that power and i didn't
notice it 
good 'ol cut and paste - it wasn't my fault! :)

anyway the resistor didn't go anywhere on one end 
and in the usual mad proto rush it was shipped because the 
DRC was happy

does DXP catch this ?

BTW, this is not a 'single pin net' since the netlist shows 2
items:
+12V2
R112-2

the 'isolated' power port counts kind of like a 'pin'

i poked around a bit in 99SE and couldn't find a way to flag it

yes manually inspecting the netlist would have caught it and 
truthfully isn't very hard to scan through even a big net list 
for this sort of thing

and for the record ...
at one time i may have been in the DXP-basher camp (some time ago)

at this point since i have not used DXP much i don't think it would 
be objective or fair for me to bash 
i hope i have not lately presented such an attitude

i would prefer to be categorized as simply a non-DXP user who is 
very reluctant to 'move on' based on what i saw during a few
brief forays 

when 2004 ships i intend to give it another go

Dennis Saputelli


Tony Karavidas wrote:
 
 There are so many reasons voiced as to why to not move to DXP.
 Here is one reason TO MOVE to DXP. It now checks for that error.
 
 Tony
 
  -Original Message-
  From: Website Visitor [mailto:[EMAIL PROTECTED]
  Sent: Friday, December 19, 2003 6:29 AM
  To: proteledaforum
  Subject: [PEDA] Protel 99SE ERC
 
  This is a little hard to explain, but here goes...
 
  I am running the ERC on a schematic in Protel 99SE.  It's
  interesting that there isn't a rule for determining whether a
  port has a mating counterpart.  The Orcad ERC has a place
  where it will verify that all off-page connectors have mating
  counterparts.  The only thing Protel 99 verifies is that the
  port is connected to something electrical.  If you had a port
  that was supposed to match a port on another page, but you
  mispelled one of them, had a space in one of them, etc. you
  wouldn't know it by using the ERC.  That seems really strange to me!
  Posted from Association web site by: Travis
 

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2851 21st StreetFax: 415-647-3003
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Re: [PEDA] Utility to count SMD/Through-hole components

2003-11-22 Thread Dennis Saputelli
this doesn't show component count of each type which is what started 
this thread and which is a cost driver for assembly rather than bare bd
fab

Dennis Saputelli


Tony Karavidas wrote:
 
 I agree with you. It's just to get them close either with stuffing the
 board, or making the PCB.
 
 Who cares if a surface mount part has a couple through hole alignment holes?
 They are holes nevertheless and require drilling, so they need to be counted
 as through holes.
 
 Here's a sample from one of my recent boards. I consider this to have
 6+(750-608)+190=338 through holes and 608 SMT pads. 6 of the through hole
 pads are not plated. What's the big deal?
 
  Layer PairVias
 
  Top Layer - Bottom Layer   190
 
  Total  190
 
  Non-Plated Hole Size  PadsVias
 
  125mil (3.175mm) 6   0
 
  Total6   0
 
  Plated Hole Size  PadsVias
 
  0mil (0mm) 608   0
  28mil (0.7112mm)25 190
  32mil (0.8128mm) 6   0
  35mil (0.889mm) 24   0
  40mil (1.016mm) 30   0
  43mil (1.0922mm)19   0
  60mil (1.524mm)  4   0
  80mil (2.032mm) 18   0
  90mil (2.286mm) 16   0
 
  Total  750 190
 
 -Original Message-
 From: Steve Wiseman [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, November 19, 2003 3:08 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Utility to count SMD/Through-hole components
 
 19/11/2003 21:45:18, Abd ul-Rahman Lomax [EMAIL PROTECTED] wrote:
 
 However, another, perhaps more practical and safer alternative
 would be to
 generate three lists: SMT, through-hole, and possibly mixed.
 The large
 majority of components would orginarily not be ambiguous.
 
 Since this is all to generate a highly suspect quote from a board- stuffing
 shop, such care is almost certainly wasted. I can't believe that a quote
 based on a QFP being costed the same as an 0805 is anything but budgetary...
 
 Sounds to me like sorting the BOM based on footprint will get the answer as
 accurately as is needed for this...
 
 Steve

-- 
Dennis Saputelli

  = send only plain text please! - no HTML ==
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Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP

2003-11-22 Thread Dennis Saputelli

yes, it is rather 'exciting' isn't it?
guess it depends on what you mean by 'exciting' 

i think it all smells pretty bad too
unfortunately it is highly consistent with their development history, 
although their business practices have morphed a bit

i must say though that for someone like myself who was not happy with 
the bugs and shortcomings which could have been easily addressed but 
were left in 99SE, 99SE's makeover as DXP, the falsehoods propagated 
about the Situs router, etc etc.
i am beginning to think that i have only myself to blame for not 
having gone elsewhere long ago

however, i will not join any class action action as i am opposed 
to them as a matter of principle 

i wonder if we would be better off if Altium had stuck by their 
Total Care or whatever it was called
Maybe they wouldn't have to chase new seats so hard. 
(idle and pointless speculation here, sorry)

acad offers some interesting parallels:
they added some features (forget catchy name) which was some 
sort of interactive internet crap 
for each of the last few upgrades the first thing i had to do was turn
off 
most of the NEW internet related features and helpers

As i understand it (I have not upgraded to ACAD2004)
ACAD2004 is a very compelling upgrade though!  :) :)
they changed some colors of some menus
they made the license much more restrictive
they removed SAVE AS release 14 (which is probably what most people use)

Dennis Saputelli

JaMi Smith wrote:
 
 What the #$%@ is going on now ? ? ?
 
 Can anyone out there understand any of this, or is this just more Protel
 / Altium Jabberwake.
 
 On one hand it looks like they are trying to make a case for making a
 new product out of something that they were supposed to give us as part
 of DXP and nVisage to begin with, and on the other hand it seems that
 they are going to end up trying to charge us money to even fix (oops,
 they will never fix it - so I guess that the more correct word would be
 finish) DXP SP3.5 (build 18550372).
 
 Maybe I just need to get a good nights sleep before I try and read this
 thing again.
 
 On the other hand, maybe we just need to nuke Australia - well maybe not
 the whole Country, but at least Protel / Altium.
 
 I think it may once again be time to wake the sleeping giant of customer
 / user opinion, but this time, unlike before when Altium supposedly
 abandoned ATS (only to re-clothe it as so clearly shown below), maybe we
 need to do it in a much more coordinated manner, that guarentees the
 outcome in writing.
 
 And what the #$%@ is Protel 2004.
 
 Could this possibly be Service Pack 7 ? ? ?
 
 What is with these guys. Is there something about all of the blood
 pooling in their brains as they stand upside down on the bottom of the
 world, or what ? ? ?
 
 Protel 99 SE is still incomplete, and needs some patches ! ! !
 
 DXP / nVisage has been lost in la la land for months and months and
 months, and still can't route a board to completion ! ! !
 
 Does anyone else out there besides me think that it is about time that
 Protel / Altium needs to come up with some real good answers.
 
 Maybe it is just about time to call a lawyer or two, and get a good
 class action lawsuit going here for SP7, SP8, SP9 and the Source Code
 for 99SE, and not only a full refund for DXP, but also some very very
 large punitive damages to cover the purchase of and retraining on some
 other EDA Software as a real solution to our EDA problems and woes.
 
 Needless to say, this is posted here, and not in the DXP Technical
 Forum, so I don't get banned once again for speaking the truth and
 seeking honest answers to honest questions.
 
 Seriously, I am not just writing this to provoke an answer from Ian or
 Abd or Tony, and in fact I beg you guys not to take this off topic and
 run it all downhill into the gutter as has been done in the past.
 
 We who are DXP Licensees have spent a very very long time waiting for
 Protel / Altium to fix the major problems in DXP, and have had no
 response to many many questions regarding the status of DXP, only now to
 find out that they have apparently not been busy trying to fix the
 problems with DXP, but coming up with something new for which they will
 ask us for more money.
 
 For those who did not get a copy, please read the original announcement
 below.
 
 The one that really really really has me fuming is the statement 
 Updates and enhancements that were under development as part of Service
 Pack 3 for nVisage and Protel will not be released for the DXP versions,
 but have now been integrated into the nVisage 2004 and Protel 2004
 releases.
 
 Protel / Altium - I don't think that you really know what you are
 getting yourself in for, and you might want to rethink your whole
 approach about selling your customer base a non functional system, and
 then turning around and saying that you are not going to fix it.
 
 JaMi Smith
 
 @ @ @ @ @ @ @ @ @ @
 
 - Original Message -
 From: Phil Loughhead [EMAIL PROTECTED

Re: [PEDA] Utility to count SMD/Through-hole components

2003-11-19 Thread Dennis Saputelli
are you speaking of the schematic BOM or the PCB BOM ?
either way there is no way (that i know of) to automatically distinguish
an SMD part from a TH part

perhaps if the schematic part had a part field filled out SMD or TH it
would be a help

since to build your bd you will need to construct a detailed BOM anyway
it shouldn't be too much work to go through and tally them up

Dennis Saputelli

Adeel Malik wrote:
 
 Hi All,
  The Protel 99SE has a Report Generating Mechanism for BOM creation.
 I want an add-on utility or a process script that can separately count the
 number of SMD and Through-hole components. Can someone comment on it ?.
 
 Regards,
 ADEEL MALIK
 

-- 
Dennis Saputelli

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Re: [PEDA] Another UF found - update

2003-11-19 Thread Dennis Saputelli
yeah i agree (although i haven't seen this particular bug)

'just say no' to the protel text editor

it's not very good and too idiosyncratic anyway

and yes UltraEdit is the best!

Dennis Saputelli


Steve Wiseman wrote:
 
 18/11/2003 20:35:57, Leo Potjewijd [EMAIL PROTECTED] wrote:
 
 I just thought I'd mention it: updating the printer driver with the
 latest
 one from the HP website does not resolve the problem
 completely. The system
 no longer crashes, but the weird output is still there..
 
 Yeah - I've seen this here. Waste of paper, isn't it
 (running into a Xerox NC20, Postscript - and, naturally, the duff
 print job makes it select the A3 tray, for maximum annoyance).
 These days, I just cut  paste into Ultraedit, which behaves rather
 better...
 

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Dennis Saputelli

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Re: [PEDA] Utility to count SMD/Through-hole components

2003-11-19 Thread Dennis Saputelli
smd pad count is usually wanted (for quote purposes) for test reasons
(SMD pad count can be reckoned easily from BOARD INFORMATION report)

drill hole count these days is usually not a factor unless holes per 
square inch exceed some very high densisty which is not typically 
encountered (possibly in very high volume it could be different)

the reason is that the production throughput bottleneck is in the 
plating tanks not the drilling so nowdays i have found the 
quotes are almost strictly based on square inches

BTW, a friend of mine recently visited a shop in China 
it was 100K+ square feet with 2 rows of drill machines extending 
as far as the eye could see
the machines were running 24/7 for the last 2 years and were just 
starting to approach payoff of the drills

re the SMD/TH part count ...
i can't imagine that it would take more than a few minutes cruising 
through even a rough BOM to come up with numbers adequate for the
purpose


Dennis Saputelli

Abd ul-Rahman Lomax wrote:
 
 At 05:35 AM 11/19/2003, Leo Potjewijd wrote:
 At 19/11/2003 01:09, Abd ul-Rahman Lomax wrote (among other things):
 [a list of assumptions]
 
 I must say that these statements are not entirely correct: many SMD
 connectors need holes in the PCB for positioning or letting the mating
 part through.
 I regularly use a http://www.avx.com/docs/Catalogs/6207.pdfFFC connector
 that has pegs for positioning and strain relief. You will need two
 non-plated holes in the PCB to accommodate that thing.
 
 First, what I wrote were presented as simplifying assumptions, not as
 necessary truths. Secondly, you need the holes, but you don't necessarily
 need a pad. Protel will allow you to use a via. However, there is no
 provision for an unplated via, so one might need to manually ensure that
 a via with hole size exceeding the diameter is not plated.
 
 This isn't very satisfactory, however, because it would involve modifying
 footprints just so that report generation would be a little easier. Better
 to generate reports for all three logical types (pure SMT, pure
 through-hole, mixed).
 
 Note, however, that there is an additional complication, which is that
 there can be a component which is neither SMT nor through-hole, it is a
 non-assembled device for accomplishing some purpose other than providing a
 place for assembly. It might be a test point, it might be a component with
 no holes whatever, representing something not fastened to the board but to,
 for example, an adjacent board, and one wants to place a dummy footprint
 and lock it in place to keep the space clear.
 
 The most likely reason the fab house asked for the pincounts is
 calculation of the bare PCB price (at least, my boardhouse does use this
 info for that purpose): holes need to be drilled, many different sizes
 and/or really small ones result in greater setup/machine/handling time.
 In electrical testing, SMD pads most likely need a different test setup:
 thru-hole pads can be accessed on both sides of te PCB while SMD pads can
 not, SMD on both sides will thus result in higher cost.
 
 The question was directly posed by Mr. Malik and it was explicitly about
 an add-on utility or a process script that can separately count the number
 of SMD and Through-hole components.
 
 It's not likely Mr. Malik was asking in response to a fabricator query,
 because fabricators have little need to know the number of surface pads;
 surface pads are merely copper features and openings in the solder mask;
 however, if the question was about pads, he asked the wrong question. It's
 easy to get a pad report, use Edit/Export to Spread.
 
 I do notice that Advanced Circuits asks about SMD pads in their instant
 quote form. Oddly enough, they *don't* ask about holes and the variety of
 hole sizes, which would have a larger effect on price, I'd think. However,
 I do recall a conversation in which a fabricator stated that holes have
 become so cheap to drill that they are not a substantial contributor to
 cost
 
 Mr. Malik, on the other hand, made another inquiry seeking recommendations
 for assembly houses, and I'd expect an assembler to need the information
 for a quotation; it's common to see figures of so many cents per SMT
 component and so many per through-hole component
 
 For this, the information would not need to be absolutely accurate, and the
 existence of a few ambiguous components would have little or no effect on
 the cost.
 

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Dennis Saputelli

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Re: [PEDA] State of PCB (aka EDA) tool business

2003-11-03 Thread Dennis Saputelli
interesting
what is that in US$ ?
at the 12 mil level double is a lot!

good article, eh?

ds

Abd ul-Rahman Lomax wrote:
 
 At 01:03 PM 11/1/2003, Dennis Saputelli wrote:
 I don't know how many people Altium has but these days $12 mil
 gross revenue is not a huge number for an international going
 enterprise
 
 true. But the revenue for Altium, estimated based on 3rd quarter 2003
 annualized, is about double that. Still not huge.
 
  From the annual report. total revenue fiscal 2002 ending June 30, 2003,
 AU$46.75; though there was an after-tax loss of AU$7.0 million, they had a
 decent cash position and paid a dividend of AU$0.02 per share out of
 retained earnings. With a share price of about AU$0.58, that is a
 substantial dividend in these times.
 
 Altium may be able to sit at this level but it seems to me
 that a more likely scenario involves the ongoing
 dramas of swallow or be swallowed
 
 I have a sense that they are not eager to be purchased. They have a very
 strong asset to liability ratio, they don't seem to owe the company to
 anyone except the shareholders. Since they experienced sales growth in all
 their markets in the last year, in what might be difficult times, if they
 are going to be bought out, I think it would not be for cheap


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Re: [PEDA] State of PCB (aka EDA) tool business

2003-11-01 Thread Dennis Saputelli
for those interested in such things...

i just read a very interesting article in 
EETIMES magazine Oct 27 2003 (an actual paper printed copy)
Gentrification hits pcb tools

Among many other things they show a chart (source: Gartner Dataquest)

TOP 20 pcb/MCM/hybrid software companies 1996 vs. 2002

http://img.cmpnet.com/eet/news/03/october/NF1293_TABLE.gif

as you can see and as they also point out the gap between 
#3 and #4 in 2002 is HUGE

You also will learn how the top vendors are doing their VeriBest :) 
to drive prices up and how there are no new entrants

I don't know how many people Altium has but these days $12 mil 
gross revenue is not a huge number for an international going
enterprise

ominous sub headings
Consolidation squeezes board tools

also some interesting history re CCT  Orcad acquisitions

full article link
http://www.eedesign.com/story/OEG20031027S0069

Altium may be able to sit at this level but it seems to me 
that a more likely scenario involves the ongoing 
dramas of swallow or be swallowed 

Dennis Saputelli

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