Re: [PEDA] Schematic Title Block - Please Explain
There is a special string for 'doc_file_name_no_path'. This is what i prefer on my templates. Have a great day Duane Thx, just what I have been looking for. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
From memory it was a JPEG image. It worked a lot better when it was converted to a .BMP Cheers, Mark Harrison Bionic Ear Institute Careful, this can change from printer driver to printer driver. IE: in my case, a postscript driver would work good, but with my laser printer in HP mode, it would completely mess up. The .jpg issue is related to jpeg's background color setting which differs from paint package to paint package. If you need a hi-res logo in the MB with a .bmp you get the color/blanks area wrong color chunks, try loading then saving you logo in an alternate paint software. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
There is a special string for 'doc_file_name_no_path'. This is what i prefer on my templates. Have a great day Duane -Original Message- From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] Sent: Thursday, October 07, 2004 10:48 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Title Block - Please Explain While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC _ This e-mail has been scanned for viruses by MCI's Internet Managed Scanning Services - powered by MessageLabs. For further information visit http://www.mci.com --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE=20HTML=20PUBLIC=20-//W3C//DTD=20HTML=203.2//EN HTML HEAD META=20HTTP-EQUIV=3DContent-Type=20CONTENT=3Dtext/html;=20 charset=3Dus= -ascii META=20NAME=3DGenerator=20CONTENT=3DMS=20Exchange=20Server =20version=20= 6.5.7036.0 TITLESchematic=20Title=20Block=20-=20Please=20Explain/TITLE /HEAD BODY !--=20Converted=20from=20text/rtf=20format=20-- P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= Hi=20all,/FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= I/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D en-usFONT= =20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG =3Den-us= /SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial m=20having=20= trouble=20wrapping=20my=20head=20around=20the=20Schematic=20ti tle=20block=20= in=2099SE./FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FA CE=3DArial= I=20don/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LA NG=3Den-us= FONT=20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN= 20LANG=3Den= -us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3D Arialt=20h= ave=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LAN G=3Den-us= =20FONT=20SIZE=3D2=20FACE=3DArial#8216;/FONT/SPANSPA N=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3 DArialDef= aul/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D en-usFON= T=20SIZE=3D2=20FACE=3DArialt/FONT/SPANSPAN=20LANG=3De n-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20t emplate/FON= T/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us FONT=20SIZE= =3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den- us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20fil e=20loaded=20= (under=20Tools-gt;Preferences)./FONT/SPANSPAN=20LANG=3D en-us/SPA= NSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial This=20setti= ng=20gives=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPA N=20LANG=3D= en-us=20FONT=20SIZE=3D2=20FACE=3DArialsimple/FONT/SPA NSPAN=20LA= NG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20 FACE=3DAria= l=20title=20block/FONT/SPANSPAN=20LANG=3Den-us/SPAN SPAN=20LAN= G=3Den-usFONT=20SIZE=3D2=20FACE=3DArial/FONT/SPANS PAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FA CE=3DArial= with=20no=20graphics=20etc.=20Nice,=20I/FONT/SPANSPAN=20 LANG=3Den
Re: [PEDA] Schematic Title Block - Please Explain
Terry, The simplest way is to use the ANSI title block. It is slightly larger than the standard. The ANSI does not have the extra text strings such as .DOC_FILE_NAME, or .DOC_FILE_NAME_NO_PATH So you will have to add them in. ANSI works for all sheet sizes. If it is too big, then you will neet to create the template for each sheet size. Much like the other replys stated. Rick -Original Message- From: Terry Creer [mailto:[EMAIL PROTECTED] Sent: Thursday, October 07, 2004 7:21 PM To: 'Protel EDA Forum' Subject: [PEDA] Schematic Title Block - Please Explain This is a multi-part message in MIME format. --=_NextPartTM-000-58042338-c6ad-48bd-9fa3-eb235d3429b6 Content-Type: multipart/alternative; boundary==_NextPart_000_001C_01C4AD2D.08FA9530 --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE HTML PUBLIC -//W3C//DTD HTML 3.2//EN HTML HEAD META HTTP-EQUIV=3DContent-Type CONTENT=3Dtext/html; = charset=3Dus-ascii META NAME=3DGenerator CONTENT=3DMS Exchange Server version = 6.5.7036.0 TITLESchematic Title Block - Please Explain/TITLE /HEAD BODY !-- Converted from text/rtf format -- P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 FACE=3DArialHi = all,/FONT/SPAN/P P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialI/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialm having trouble wrapping my head around the Schematic = title block in 99SE./FONT/SPAN/P P ALIGN=3DLEFTSPAN LANG=3Den-usFONT SIZE=3D2 FACE=3DArialI = don/FONT/SPANSPAN LANG=3Den-us/SPANSPAN LANG=3Den-usFONT = SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialt have a/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArial#8216;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialDefaul/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArialt/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial template/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial file loaded (under = Tools-gt;Preferences)./FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArialThis setting gives = a/FONT/SPANSPAN LANG=3Den-us/SPANSPAN LANG=3Den-us FONT = SIZE=3D2 FACE=3DArialsimple/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial title block/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArialwith no graphics etc. = Nice, I/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-usFONT SIZE=3D2 FACE=3DArial#8217;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArialm happy/FONT/SPANSPAN LANG=3Den-us/SPANSPAN = LANG=3Den-us FONT SIZE=3D2 FACE=3DArial#8211;/FONT/SPANSPAN = LANG=3Den-us/SPANSPAN LANG=3Den-usFONT SIZE=3D2 = FACE=3DArial except for one thing/FONT/SPANSPAN = LANG
Re: [PEDA] Schematic Title Block - Please Explain
Yeh, but watch out what you replace the logo with - I once replaced it with my own logo, which looked nice on the screen, but randomly screwed up printing. It took weeks to make the connection between changing the logo and discovering why wires and labels were occasionally moving all over the printed pages! From memory it was a JPEG image. It worked a lot better when it was converted to a .BMP Cheers, Mark Harrison Bionic Ear Institute -Original Message- From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] Sent: Friday, October 08, 2004 3:48 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Title Block - Please Explain While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic Title Block - Please Explain
This is a multi-part message in MIME format. Title: Schematic Title Block - Please Explain Hi all, Im having trouble wrapping my head around the Schematic title block in 99SE. I dont have a Default template file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, Im happy except for one thing the filename has its full path displayed and more often than not extends into and way past the Drawn By box. The other nice thing about this title block is that I can go into Document Options and change the template size and the title block always stays in the bottom right-hand corner. So my first question is where is this title block stored so I can modify it (if possible)? Now when I load a Default Template from Tools - Preferences it has the big Protel logo with Protels full address etc, etc on it. I dont remember working for Protel At least I dont think I do These templates are no good to me. These are the ones in the Templates.ddb. I realize I can generate my own template, but that brings up another problem resizing the sheet on the fly. If I use a custom template and change its size with Document Options, then the title block stays where it is (it doesnt stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is is a custom template for every sheet size I use the only way? All I want is the standard template without the full file path displayed in it. Is this asking too much? Sorry about the longwinded spiel, but I think this is important and its been bugging me for a long time. Thanks in advance for any guidance, TC
Re: [PEDA] Schematic Title Block - Please Explain
Ugh, Sorry about the garbled crap - Office keeps insisting on HTML messages - should be fixed now... TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
The title block is stored in the sheet template. The sheet templates are in xx\Design Explorer 99SE\System\Templates.ddb Open a template, edit the desired elements, save the result as a .dot file with a file name of your choosing, then reuse it anytime as the template for your own custom sheet. If you change the template on-the-fly you can save as .dot file and reuse it. Yes - you have to have a separate template for each size sheet you commonly use. At 07:20 PM 10/7/04, you wrote: Hi all, Im having trouble wrapping my head around the Schematic title block in 99SE. I dont have a Default template file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, Im happy except for one thing the filename has its full path displayed and more often than not extends into and way past the Drawn By box. The other nice thing about this title block is that I can go into Document Options and change the template size and the title block always stays in the bottom right-hand corner. So my first question is where is this title block stored so I can modify it (if possible)? Now when I load a Default Template from Tools - Preferences it has the big Protel logo with Protels full address etc, etc on it. I dont remember working for Protel At least I dont think I do These templates are no good to me. These are the ones in the Templates.ddb. I realize I can generate my own template, but that brings up another problem resizing the sheet on the fly. If I use a custom template and change its size with Document Options, then the title block stays where it is (it doesnt stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is is a custom template for every sheet size I use the only way? All I want is the standard template without the full file path displayed in it. Is this asking too much? Sorry about the longwinded spiel, but I think this is important and its been bugging me for a long time. Thanks in advance for any guidance, TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Title Block - Please Explain
While editing a template you can edit all graphics on it as well, so you can delete Protel logo if you wanted. You can also delete a special string, which is in your case file path. The template has to be opened as a .dot file. Cheers, Igor Hi all, I'm having trouble wrapping my head around the Schematic title block in 99SE. I don't have a 'Default template' file loaded (under Tools-Preferences). This setting gives a simple title block with no graphics etc. Nice, I'm happy - except for one thing - the filename has its full path displayed and more often than not extends into and way past the 'Drawn By' box. The other nice thing about this title block is that I can go into 'Document Options' and change the template size and the title block always stays in the bottom right-hand corner. So my first question is - where is this title block stored so I can modify it (if possible)? Now when I load a 'Default Template' from Tools - Preferences it has the big Protel logo with Protel's full address etc, etc on it. I don't remember working for Protel. At least I don't think I do. These templates are no good to me. These are the ones in the 'Templates.ddb'. I realize I can generate my own template, but that brings up another problem - resizing the sheet on the fly. If I use a custom template and change it's size with 'Document Options', then the title block stays where it is (it doesn't stay in the bottom right hand corner). Useless. That means I have to make a template for every size of sheet I want? Eugh. So I guess my second question is - is a custom template for every sheet size I use the only way? All I want is the 'standard' template without the full file path displayed in it. Is this asking too much? Sorry about the long-winded spiel, but I think this is important and it's been bugging me for a long time. Thanks in advance for any guidance, TC _ This e-mail has been scanned for viruses by MCI's Internet Managed Scanning Services - powered by MessageLabs. For further information visit http://www.mci.com --=_NextPart_000_001C_01C4AD2D.08FA9530 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: quoted-printable !DOCTYPE=20HTML=20PUBLIC=20-//W3C//DTD=20HTML=203.2//EN HTML HEAD META=20HTTP-EQUIV=3DContent-Type=20CONTENT=3Dtext/html;=20charset=3Dus= -ascii META=20NAME=3DGenerator=20CONTENT=3DMS=20Exchange=20Server=20version=20= 6.5.7036.0 TITLESchematic=20Title=20Block=20-=20Please=20Explain/TITLE /HEAD BODY !--=20Converted=20from=20text/rtf=20format=20-- P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= Hi=20all,/FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= I/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT= =20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den-us= /SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialm=20having=20= trouble=20wrapping=20my=20head=20around=20the=20Schematic=20title=20block=20= in=2099SE./FONT/SPAN/P P=20ALIGN=3DLEFTSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial= I=20don/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us= FONT=20SIZE=3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den= -us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialt=20h= ave=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-us= =20FONT=20SIZE=3D2=20FACE=3DArial#8216;/FONT/SPANSPAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArialDef= aul/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFON= T=20SIZE=3D2=20FACE=3DArialt/FONT/SPANSPAN=20LANG=3Den-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20template/FON= T/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE= =3D2=20FACE=3DArial#8217;/FONT/SPANSPAN=20LANG=3Den-us/SPAN= SPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial=20file=20loaded=20= (under=20Tools-gt;Preferences)./FONT/SPANSPAN=20LANG=3Den-us/SPA= NSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArialThis=20setti= ng=20gives=20a/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D= en-us=20FONT=20SIZE=3D2=20FACE=3DArialsimple/FONT/SPANSPAN=20LA= NG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DAria= l=20title=20block/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LAN= G=3Den-usFONT=20SIZE=3D2=20FACE=3DArial/FONT/SPANSPAN=20LANG=3D= en-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial= with=20no=20graphics=20etc.=20Nice,=20I/FONT/SPANSPAN=20LANG=3Den-u= s/SPANSPAN=20LANG=3Den-usFONT=20SIZE=3D2=20FACE=3DArial#8217;= /FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20= SIZE=3D2=20FACE=3DArialm=20happy/FONT/SPANSPAN=20LANG=3Den-us/= SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3DArial#8211;/= FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3Den-usFONT=20S= IZE=3D2=20FACE=3DArial=20except=20for=20one=20thing/FONT/SPANSPAN=20= LANG=3Den-us/SPANSPAN=20LANG=3Den-us=20FONT=20SIZE=3D2=20FACE=3D= Arial#8211;/FONT/SPANSPAN=20LANG=3Den-us/SPANSPAN=20LANG=3D=
Re: [PEDA] Schematic text back to front and upside down
Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Use a mirror to read it?? Cheers, MvdW * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
[PEDA] Schematic text back to front and upside down
Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Using Protel 99SE SP6 on Windows XP home SP1 Latest Brother printer drivers installed. Regards, Kat. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 24/01/2004 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic text back to front and upside down
Kathy Quinlan wrote: Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Clearly, your printer driver is bad. See if Brother has a new driver you can download. If the printer is an emulator for some other brand (HP, Epson, etc.) try a few different drivers for the emulated brand to see if one of them corrects the problem. I once had to send a laser printer back and get a different make as the PostScript emulator in it had a defect that smashed text from a particular application. The maker admitted the problem was bad firmware in the printer, but they had no practical way to fix it. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic text back to front and upside down
Sounds like you have checked the mirrored text box - Original Message - From: Kathy Quinlan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, February 04, 2004 11:06 AM Subject: [PEDA] Schematic text back to front and upside down Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Using Protel 99SE SP6 on Windows XP home SP1 Latest Brother printer drivers installed. Regards, Kat. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 24/01/2004 This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic text back to front and upside down
Wow Is that like rotated, or reversed and inverted? Rob Gillatt - Original Message - From: Kathy Quinlan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, February 04, 2004 4:06 PM Subject: [PEDA] Schematic text back to front and upside down Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Using Protel 99SE SP6 on Windows XP home SP1 Latest Brother printer drivers installed. Regards, Kat. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 24/01/2004 This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic text back to front and upside down
On 03:06 AM 5/02/2004, Kathy Quinlan said: Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. I use a Brother HL1450 - very similar mechanically but I am not sure if the printer languages are the same. The 1440 doesn't have PostScript, I think and the version of PCL may not be the same as in the 1450 (PCL 6 on the 1450). But my 1450 works very well - on Sch, PCB (both P99SE and DXP) and pretty much anything else we throw at it. I use WinXP Pro now and previously Win2000. As a test, can you make a PDF and try printing that. Do you have any other printer you can try printing on? Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic text back to front and upside down
Does Preview show the problem? Rob Gillatt - Original Message - From: Kathy Quinlan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, February 04, 2004 4:06 PM Subject: [PEDA] Schematic text back to front and upside down Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Using Protel 99SE SP6 on Windows XP home SP1 Latest Brother printer drivers installed. Regards, Kat. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 24/01/2004 This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Schematic Symbol Import
-Original Message- From: Steve Smith [mailto:[EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 4:09 PM To: [EMAIL PROTECTED] Subject: [PEDA] Schematic Symbol Import Is there a way to import Mentor or EDIF schematic symbols into DXP? I have found schematic symbols on Motorola's web site. I'm really trying to avoid drawing symbols for a 783 pin device. Steve Which part on Mots site are you trying to convert? Can you give me the URL? John * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Symbol Import
John, Here's the url: http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540 About 3/4 down is a schematics section for part symbols. I'm wondering if there is a way to import these. Thanks, Steve -Original Message- From: John A. Ross [Design] [mailto:[EMAIL PROTECTED] Sent: Thursday, January 08, 2004 4:54 AM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Symbol Import -Original Message- From: Steve Smith [mailto:[EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 4:09 PM To: [EMAIL PROTECTED] Subject: [PEDA] Schematic Symbol Import Is there a way to import Mentor or EDIF schematic symbols into DXP? I have found schematic symbols on Motorola's web site. I'm really trying to avoid drawing symbols for a 783 pin device. Steve Which part on Mots site are you trying to convert? Can you give me the URL? John * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Symbol Import
Steve I already found it from your post in the DXP list. I have tried to open these files and export a Orcad library for you but I keep getting an error on export. The orcad librray you could open in DXP. I have asked my colleague in Spain who uses Board Architect if he can open the Mentor files and re-export them. But I wont get an answer till tommorrow. But I think that's quicker than editing all pins by hand. As an alternative, I have asked him to give me a CSV dump of the pin list and you could use the speadsheet method in DXP to create the part. Will get back to you tomorrow Best Regards John A. Ross RSD Communications ltd Email [EMAIL PROTECTED] WWWhttp://www.rsd.tv == -Original Message- From: Steve Smith [mailto:[EMAIL PROTECTED] Sent: Thursday, January 08, 2004 2:39 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Schematic Symbol Import John, Here's the url: http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?cod e=MPC8540 About 3/4 down is a schematics section for part symbols. I'm wondering if there is a way to import these. Thanks, Steve -Original Message- From: John A. Ross [Design] [mailto:[EMAIL PROTECTED] Sent: Thursday, January 08, 2004 4:54 AM To: Protel EDA Forum Subject: Re: [PEDA] Schematic Symbol Import -Original Message- From: Steve Smith [mailto:[EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 4:09 PM To: [EMAIL PROTECTED] Subject: [PEDA] Schematic Symbol Import Is there a way to import Mentor or EDIF schematic symbols into DXP? I have found schematic symbols on Motorola's web site. I'm really trying to avoid drawing symbols for a 783 pin device. Steve Which part on Mots site are you trying to convert? Can you give me the URL? John * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic Symbol Import
Is there a way to import Mentor or EDIF schematic symbols into DXP? I have found schematic symbols on Motorola's web site. I'm really trying to avoid drawing symbols for a 783 pin device. Thanks, Steve Smith * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic component parts swapping around...
Hey all, An interesting problem - P99se SP6, Win2000: I've made myself a custom LM393 schematic component. This is a dual open collector comparator, consisting of two parts, 1 and 2. On occasion, Protel seems to be swapping component parts around on me. Part 1 becomes a part 2, etc This has happened twice now. It happened a few minutes ago, when I had just placed the components in the schematic, no wiring or anything, and went to do an annotation. It also happened once a few days ago when it swapped parts around that were already numbered and in circuit. I'm not sure exactly when it did that, I just noticed they were swapped a few days ago when going throught the schematic sheet looking for something else. Its a new schematic file, but with part of the design cut and pasted from another design. Most of the components I'm using are from the existing design too. I have only 3 other multi part components in this design, and they don't appear to be swapping about. I did not make these two, I exported them from an existing schematic.. I'm pretty sure that there is nothing weird about the schematic component I made, but then, why is it the one being stuffed around like this? Has anyone had this happen to them before? if so, how do I fix the problem and stop it from hapenning again? Please help, I don't like the idea of component parts swapping around randomly on me!!! thanks, Julian -- Julian Higginson - Design Engineer - Lake Technology. 502/51-55 Mountain St, Ultimo, NSW, 2007, Australia. mailto:[EMAIL PROTECTED] - http://www.lake.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic component parts swapping around...
Julian, The parts will (can) swap when you re-annotate the schematic the best you can do is get them the way you want them and only re-annotate '?' parts after that. Darren Moore -Original Message- From: Julian Higginson [mailto:[EMAIL PROTECTED]] Hey all, An interesting problem - P99se SP6, Win2000: I've made myself a custom LM393 schematic component. This is a dual open collector comparator, consisting of two parts, 1 and 2. On occasion, Protel seems to be swapping component parts around on me. Part 1 becomes a part 2, etc This has happened twice now. It happened a few minutes ago, when I had just placed the components in the schematic, no wiring or anything, and went to do an annotation. It also happened once a few days ago when it swapped parts around that were already numbered and in circuit. I'm not sure exactly when it did that, I just noticed they were swapped a few days ago when going throught the schematic sheet looking for something else. Its a new schematic file, but with part of the design cut and pasted from another design. Most of the components I'm using are from the existing design too. I have only 3 other multi part components in this design, and they don't appear to be swapping about. I did not make these two, I exported them from an existing schematic.. I'm pretty sure that there is nothing weird about the schematic component I made, but then, why is it the one being stuffed around like this? Has anyone had this happen to them before? if so, how do I fix the problem and stop it from hapenning again? Please help, I don't like the idea of component parts swapping around randomly on me!!! thanks, Julian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic component parts swapping around...
Hey Darren, The parts will (can) swap when you re-annotate the schematic the best you can do is get them the way you want them and only re-annotate '?' parts after that. thanks for the info. I only ever annotate '?' parts, and I'm very sure that the first parts I'd noticed were swapped had already been given designators before they got swapped but I could be mistaken. I hope so. Strange though - I've never noticed this behaviour with Protel before, and I've placed a fair few multi part components before it always managed to keep the component parts right in the positions I'd left them, even if it doesn't always group the parts with the same designators I'd always like... thanks, Julian -- Julian Higginson - Design Engineer - Lake Technology. 502/51-55 Mountain St, Ultimo, NSW, 2007, Australia. mailto:[EMAIL PROTECTED] - http://www.lake.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic Creation/Read error: File Format Not Recognized
I'm just started getting a File Format not recognized error upon creating new or attempting to read certain schematic files within P99SE/6. I though that there might be some sort of problem with the file association on .Sch, but that does not _appear_ to be the problem. I checked Protel's KB with no luck (perhaps bad search terms, but I'm not sure). Only one hit for File format not recognized with no pertinent info contained therein. Anyone have a clue to share or pointer to solution? Is this a known problem? Corrupted resource or ini file(s)? Time to re-install? TIA, aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Creation/Read error: File Format Not Recognized
Hi AJ I've only ever seen this when the schematic template file is moved or corrupt. Try removing any special templates or checking your created ones (if applicable) Hope that helps Rich -Original Message- From: [EMAIL PROTECTED] [mailto:ajenkins;avtron.com] Sent: 04 November 2002 18:18 To: Protel EDA Forum Subject: [PEDA] Schematic Creation/Read error: File Format Not Recognized I'm just started getting a File Format not recognized error upon creating new or attempting to read certain schematic files within P99SE/6. I though that there might be some sort of problem with the file association on .Sch, but that does not _appear_ to be the problem. I checked Protel's KB with no luck (perhaps bad search terms, but I'm not sure). Only one hit for File format not recognized with no pertinent info contained therein. Anyone have a clue to share or pointer to solution? Is this a known problem? Corrupted resource or ini file(s)? Time to re-install? TIA, aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic - Global replace for Lib ref field
At 05:53 PM 9/16/2002 -0700, Brad Velander wrote: are you aware that you must put the copied data in the copy attributes box where it appears on the horizontal row. For those fields that have this box, the copied data (in this case the symbol name) must appear in this box. Replace the brackets with your new symbol name. Anyone have an idea why Schematic insists on this whereas PCB uses a much simpler system which essentially automatically takes edited data and uses it as the new data, which is what we want most of the time. Partial replacement is nice, but it is not what we need in the large majority of edits, and I think we could have both. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic order
This peaked my curiosity. I overlaped the corners of each of the sheet blocks. The draw order is now visible as any sheet not in the correct order does not tile correctly with it's neighbor. If you use the sheets as order markers only, this works out great as a graphical hierarchy. Thanks for the tip. -Original Message- From: Rob Young [mailto:[EMAIL PROTECTED]] Sent: Saturday, August 17, 2002 3:44 AM To: Protel EDA Forum Subject: Re: [PEDA] Schematic order Open the top level page with the sheet symbols. Edit Move Send to Back Then click on the first sheet symbol in your list, the second, and so on. The order in which they appear is based on the order in which they were placed. You will just need to use the send to back command to reorder your symbols. Rob Young - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Form [EMAIL PROTECTED] Sent: Friday, August 16, 2002 1:09 PM Subject: [PEDA] Schematic order Is there a way to change the order of sch files under a .prj file in the Design Manager Panel? I cannot click and drag them like I can my bookmarks in my web browser. Tim Fifield * Tracking #: DFEC689156063A4587C3D8F387DB1606942FC5D9 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic order
Hi,
You can highlight the sheet symbol and use EditMoveBring to front etc.
The order of files in the tree is determined from their drawing order.
/Mattias Ericson
Mattias Ericson
Omnisys Instruments AB
Gruvgatan 8
SE-421 30 Västra Frölunda, SWEDEN
Phone: +46 31 734 34 08
Fax: +46 31 734 34 29
http://www.omnisys.se
Tim Fifield
[EMAIL PROTECTED]To: Protel EDA Form
[EMAIL PROTECTED]
cc:
Subject: [PEDA] Schematic order
2002-08-16 14:09
Please respond to
Protel EDA
Forum
Is there a way to change the order of sch files under a .prj file in the
Design Manager Panel? I cannot click and drag them like I can my bookmarks
in my web browser.
Tim Fifield
* Tracking #: DFEC689156063A4587C3D8F387DB1606942FC5D9
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Re: [PEDA] Schematic order
Open the top level page with the sheet symbols. Edit Move Send to Back Then click on the first sheet symbol in your list, the second, and so on. The order in which they appear is based on the order in which they were placed. You will just need to use the send to back command to reorder your symbols. Rob Young - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Form [EMAIL PROTECTED] Sent: Friday, August 16, 2002 1:09 PM Subject: [PEDA] Schematic order Is there a way to change the order of sch files under a .prj file in the Design Manager Panel? I cannot click and drag them like I can my bookmarks in my web browser. Tim Fifield * Tracking #: DFEC689156063A4587C3D8F387DB1606942FC5D9 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic order
Is there a way to change the order of sch files under a .prj file in the Design Manager Panel? I cannot click and drag them like I can my bookmarks in my web browser. Tim Fifield * Tracking #: DFEC689156063A4587C3D8F387DB1606942FC5D9 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic order
no, (AFAIK) i wish that was there too Dennis Saputelli Tim Fifield wrote: Is there a way to change the order of sch files under a .prj file in the Design Manager Panel? I cannot click and drag them like I can my bookmarks in my web browser. Tim Fifield * Tracking #: CDF464CCCF64D943BD70866876928FEC007DCCCD * -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic order
Re: [PEDA] Schematic Import (WAS: Hot Linking)
OK, So everything seems to be ok except that when I look at a parts attributes after an import nothing seems to change. This is what I'm doing. Export 1. In Schematic Editor. FileExportExport Schematic to Database. 2. I choose Part as my selected primitive. 3. I choose X and Y Loc, Lib Ref, Footprint, Designator, Part Type as my Selected Attributes. 4. Tick Include Sheet Name. 5. Click Ok. Now I Open the Part.DBF and change only the Lib Ref on one component (R1 in this case) I save the Part.DBF and I says do you want to overwrite it? I click yes. Then it says PART.DBF may contain features that are not compatible with DBF 4 (dBASE IV). Do you want to keep the workbook in this format? (I'm thinking this may be a clue) I click yes. Then back in Protel I go. 1. FileImportImport Schematic from Database. 2. Click Part in attributes, browse to the correct database file name. 3. Import Options: Scope - Current Project, Action - Update Only 4. Mapped Attributes XYLOCATION, LIBREF, DESIGNATOR, and SHEET_PATH. 5. Set Key Fields XYLOCATION, DESIGNATOR, and SHEET_PATH. (This should mean that only the Lib Ref feild is updated, right?) 6. Click ok. 7. Wait while Protel chews away 8. When all is finished, go to R1 on schematic, double click on it and Lib Ref has not changed! RRHH! :) Somebody please tell me something I'm missing Tim * Tracking #: 1C522C924BDB6748B8134F884910BC0DB700B0C7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic Port questions
Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? Why do I care about net names? Because descriptive names help me when I'm routing. Why don't I want to add a net label? Because then I have a wire with a net label and a port right next to each other -- it just looks silly. (2) I am using the Reports/Add Port References (Flat) feature which works pretty well except that it doesn't seem to generate a reference for ports of the same name on the same page. Is there any way to get the references for ports on the same page? Thanks, Matt __ Do You Yahoo!? LAUNCH - Your Yahoo! Music Experience http://launch.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
At 12:16 PM 5/20/2002 -0700, Embedded Matt wrote: Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? If you are using a hierarchical schematic, the net will take the name that it has on the highest level on which the net occurs. If the net is not named on that level, it will be given a numerical name. This is not a bug, it is, rather, a necessary consequence of how hierarchical schematics can be used. One may connect WR* on one sheet symbol to CHANNEL1WR* on another sheet symbol. Which name do you give it? Even if the schematic is not flat, suppose one is using Ports Only scope. Using a port, one may connect a net with one name on one sheet to a net with a different name on another sheet. In other words, Net Labels establish a local name (or a global name under certain circumstances, Ports connect between sheets. Ports are not used to name nets. If you are using Net Labels and Ports Global scope, you must place a net label to force the assignment of a net name. With this scope, you don't need to use ports at all But a little redundancy never hurt anyone. Why do I care about net names? Because descriptive names help me when I'm routing. Why don't I want to add a net label? Because then I have a wire with a net label and a port right next to each other -- it just looks silly. Nevertheless, sometimes this is absolutely necessary. (2) I am using the Reports/Add Port References (Flat) feature which works pretty well except that it doesn't seem to generate a reference for ports of the same name on the same page. Is there any way to get the references for ports on the same page? I haven't used that tool, so I'll let someone else answer Except I'll mention that this is not how Ports are designed to be used. They are specifically for intersheet connections. Bring a Port onto a sheet and if you want to use it in various places without having a wire, use multiple net labels. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
[snip] Why don't I want to add a net label? Because then I have a wire with a net label and a port right next to each other -- it just looks silly. [snip] Then put the net label on the other end of the wire. In fact, I like to put net labels on both ends of the wire (sometimes in the middle a few times too) on very long wires. And why would I do that you ask? When you are wiring up a schematic with a bunch of parallel wires making 90 degree turns and snaking around components, humans have a tendency to loose the wire they are following. So if you are following a wire and find a net label along the way, you can confirm that you are on the correct wire. Jeff Stout * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
On 12:16 PM 20/05/2002 -0700, Embedded Matt said: Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? No. (2) I am using the Reports/Add Port References (Flat) feature which works pretty well except that it doesn't seem to generate a reference for ports of the same name on the same page. Is there any way to get the references for ports on the same page? There is a 3rd party port annotator available. http://www.aspiring-technology.com/ This third part server has been reported by some to be better than the in-built tool but I have not tested either so can't vouch for that. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
On 06:28 PM 20/05/2002 -0400, Abd ulRahman Lomax said: At 12:16 PM 5/20/2002 -0700, Embedded Matt wrote: Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? If you are using a hierarchical schematic, the net will take the name that it has on the highest level on which the net occurs. If the net is not named on that level, it will be given a numerical name. This is not a bug, it is, rather, a necessary consequence of how hierarchical schematics can be used. One may connect WR* on one sheet symbol to CHANNEL1WR* on another sheet symbol. Which name do you give it? Even if the schematic is not flat, suppose one is using Ports Only scope. Using a port, one may connect a net with one name on one sheet to a net with a different name on another sheet. In other words, Net Labels establish a local name (or a global name under certain circumstances, Ports connect between sheets. Ports are not used to name nets. If you are using Net Labels and Ports Global scope, you must place a net label to force the assignment of a net name. With this scope, you don't need to use ports at all But a little redundancy never hurt anyone. Maybe my No answer was less than helpful :-) On a related issue. Do you know that you can use the cloning (or morphing) facility in Protel to quickly grab the text out of a Port while placing net labels? And visa-versa (taking a netlabels text into a port while placing ports). While placing an entity hover over the thing you want to clone and press the INS key. On some objects this can be a little fiddly (getting the right spot) but with a little practice it works well. Morphing can be found in both the on-line help and the printed docs - use the online help Find and enter morph (use the index for the printed stuff). This is a very useful tool in many situations (such as going around adding all your power ports to your design). Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
--- Abd ulRahman Lomax [EMAIL PROTECTED] wrote: If you are using Net Labels and Ports Global scope, you must place a net label to force the assignment of a net name. With this scope, you don't need to use ports at all I don't? Great! But then how do I generate the little strings next to the net labels that tell me what page and grid reference the net goes to? I'll tell you how I've done it in the past -- by hand! It's time consuming and error prone, but necessary. My schematics are typically about 10 pages or so so I need an aid to help me find the other end of the wire. (When I'm debugging in the field, I'm using paper copies.) Ports allow me to automate the process but with two distinct disadvantages over my tedious manual method: 1. It seems impossible to generate references within the same page automatically (without 3rd party tools). 2. The automatically generated references sometimes appear on the wrong side of the port so that the text is placed directly over a wire. Sometimes I can fix this; sometimes I can't. Anybody have any clever ways they handle generating net cross references? I've seen schematics (not drawn in Protel) that include tables at the end with this kind of information. Although, in my opinion, that's not quite as convenient as having the information embedded on every page, if I could generate that kind of table automatically I'd adopt that method in a second. Thanks! Matt __ Do You Yahoo!? LAUNCH - Your Yahoo! Music Experience http://launch.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Port questions
At 09:03 AM 5/21/2002 +1000, you wrote: On 12:16 PM 20/05/2002 -0700, Embedded Matt said: Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? No. (2) I am using the Reports/Add Port References (Flat) feature which works pretty well except that it doesn't seem to generate a reference for ports of the same name on the same page. Is there any way to get the references for ports on the same page? There is a 3rd party port annotator available. http://www.aspiring-technology.com/ This third part server has been reported by some to be better than the in-built tool but I have not tested either so can't vouch for that. Ian Wilson This is a very good tool. A lot better than Protel's attempt. I just hope Protel put's it in their upcoming release. Positioning could be better. Something for Protel to shoot for. Rusty Garfield C. I. D. Development Technician IV Sugar Land Product Center (281) 285-7611 (voice) (281) 285-7619 (fax) [EMAIL PROTECTED] (e-mail) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
At 03:24 PM 3/26/2002 -0600, David W. Gulley wrote: When I am trying to show a multi-signal connection to a point (e.g. single point ground) I usually go non orthogonal, that is I have the symmetrical signals come into the point from an angle (not a right angle). The single point is readily apparent, and there is no confusion over whether or not a tie point is present. That is a very useful convention, quite clear and unmistakeable. However, I prefer to create star grounds using jumpers or virtual shorts, because this forces the routing into an actual star, since the legs remain distinct nets to Protel. Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
-Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: 26 March 2002 17:58 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] Schematic standards [cut] In my view, the best practice is to avoid crossed connections *and* to use connection dots on the T connections. Absolutely! Any opportunity for ambiguity is best avoided. I also remember that there are a few exceptions to the 4 way connection rule, specifically where there were symmetrical circuits involved such as a dual power supply (positive and negative) where all the capacitors came together at ground in the middle. I disagree that this is best represented with a cross wire tied with a connection dot. It is quite simple to jog one or both connections, or to stagger the capacitor placements. The former takes a little less space. The point of avoiding crossed connections is that (1) it can be read more quickly, especially if the tie dots are small and (2) errors from omitted tie dots won't happen (if floating wires are flagged with warnings). and (3) after the hard copy in the documentation becomes a nth-generation photocopy you can be sure that the blob at the crossover *isn't* meant to be a connection! (We were taught this rule a few years back in the days of dyeline prints from 'pencil on drafting film' schematics, and although modern photocopiers are a lot better it's still worth following). Regards, Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
I was taught (12 years ago) to go non-orthogonal one grid point away from the connection, and come in at 45 degrees: | | | / ---o-o- / | | | Sorry for the very bad ASCII art. The 'o' represents a junction dot. I always do this - nobody has complained. Steve. -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: 26 March 2002 17:58 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] Schematic standards [cut] In my view, the best practice is to avoid crossed connections *and* to use connection dots on the T connections. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
At 09:55 AM 3/25/2002 -0500, Watnoski, Michael wrote: Back in my early days, I was taught to never make a wire junction with 4 wires joining in an X configuration. All junctions were to be of the T configuration as the this was to assumed to be a connection, whether or not a dot was visible and the X was assumed to unconnected. Note that in normal Protel operation, it is impossible to omit a tie dot in a T connection, since the editor automatically adds a tie dot if you create a T. In order to make a crossed connection, one must deliberately wire a second wire to the original tie dot, or add a tie dot to crossed wires. The latter is somewhat unreliable. Try this: cross two wires, place a tie dot on the apparent junction, then move one of the wires. The tie dot will not move with the wire (if there are no wire ends at the crossing point), but will be left floating (it will still be on one wire, but it will not be making any connection). Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
At 10:03 AM 3/25/2002 -0800, JaMi Smith wrote: Michael, If the little grey cells are functioning properly, they tell me that it was ANSI Y14.15 and Y32.2. As for the T, all of the companies that I have worked for wanted the connection dot regardless. In my view, the best practice is to avoid crossed connections *and* to use connection dots on the T connections. I also remember that there are a few exceptions to the 4 way connection rule, specifically where there were symmetrical circuits involved such as a dual power supply (positive and negative) where all the capacitors came together at ground in the middle. I disagree that this is best represented with a cross wire tied with a connection dot. It is quite simple to jog one or both connections, or to stagger the capacitor placements. The former takes a little less space. The point of avoiding crossed connections is that (1) it can be read more quickly, especially if the tie dots are small and (2) errors from omitted tie dots won't happen (if floating wires are flagged with warnings). While I'd be tempted to disallow crossed connections entirely, I'd be content with a warning in ERC Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
Abd ul-Rahman Lomax wrote: At 10:03 AM 3/25/2002 -0800, JaMi Smith wrote: Michael, If the little grey cells are functioning properly, they tell me that it was ANSI Y14.15 and Y32.2. As for the T, all of the companies that I have worked for wanted the connection dot regardless. In my view, the best practice is to avoid crossed connections *and* to use connection dots on the T connections. I also remember that there are a few exceptions to the 4 way connection rule, specifically where there were symmetrical circuits involved such as a dual power supply (positive and negative) where all the capacitors came together at ground in the middle. I disagree that this is best represented with a cross wire tied with a connection dot. It is quite simple to jog one or both connections, or to stagger the capacitor placements. The former takes a little less space. When I am trying to show a multi-signal connection to a point (e.g. single point ground) I usually go non orthogonal, that is I have the symmetrical signals come into the point from an angle (not a right angle). The single point is readily apparent, and there is no confusion over whether or not a tie point is present. I avoid X 4-way connections, as schematics in the past have gone through many photocopy cycles and a dot on a 4-way junction disappears into the noise and dots appear where there were none. Even though PDF distribution is more prevalent, most of my clients like to know that if the signals cross, there is NO connection (regardless of there seeming to be a dot present). David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic standards
Re: [PEDA] Schematic standards
Michael, If the little grey cells are functioning properly, they tell me that it was ANSI Y14.15 and Y32.2. As for the T, all of the companies that I have worked for wanted the connection dot regardless. I also remember that there are a few exceptions to the 4 way connection rule, specifically where there were symmetrical circuits involved such as a dual power supply (positive and negative) where all the capacitors came together at ground in the middle. JaMi Smith -Original Message- From: Watnoski, Michael [mailto:[EMAIL PROTECTED]] Sent: Monday, March 25, 2002 6:55 AM To: '[EMAIL PROTECTED]' Subject: [PEDA] Schematic standards Greetings All, Back in my early days, I was taught to never make a wire junction with 4 wires joining in an X configuration. All junctions were to be of the T configuration as the this was to assumed to be a connection, whether or not a dot was visible and the X was assumed to unconnected. Does any know what standards describe these procedures? Are the standards EIA, ANSI, Military, or others? Michael * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
[PEDA] Schematic symbols
Is there a way to have vertical oriented pins have horizontal pin names numbers? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic symbols
At 10:49 AM 2/14/2002 -0500, Sean James wrote: Is there a way to have vertical oriented pins have horizontal pin names numbers? Well, you can fake it. Hide the names and/or numbers and add text strings to the symbol. Note that rotating or mirroring such a symbol can produce strange results, so if you need rotated/mirrored versions, make them as separate symbols. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic
Has anybody used the Increment part Number in a schematic? I don't see it loaded in the server list, and it doesn't seem to work in a schematic. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic PCB viewer
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Re: [PEDA] Schematic PCB viewer
If I understand the question correctly, you can tile the windows to view both at once. Tim Fifield [EMAIL PROTECTED] International Rectifier -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Friday, January 11, 2002 6:27 AM To: proteledaforum Subject: [PEDA] Schematic PCB viewer Does Protel 99SE have a viewer to view schematics and the PCB? Thanks, Mark [EMAIL PROTECTED] Posted from Association web site by: Mark Mainland * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic PCB viewer
If you are asking if there is a stand-alone viewer application (that you might send clients, for example) the answer is no. However, you can request a demo CD of Protel 99SE from Altium and that can be used to view your files. It will be a limited function version (I'm not sure of the limitations though). The way I distribute files from Protel for customer viewing is make pdf files directly from Protel using Adobe Acrobat. The customer can then view and print them, but not manipulate any design data. If the customer actually needs to manipulate data, export data, etc. -- then your only other choice is really for the customer to purchase Protel99SE. Matt Pobursky Maximum Performance Systems On Fri, 11 Jan 2002 10:27:10 Central Standard Time, [EMAIL PROTECTED] wrote: Does Protel 99SE have a viewer to view schematics and the PCB? Thanks, Mark [EMAIL PROTECTED] Posted from Association web site by: Mark Mainland * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic PCB viewer
At 01:20 PM 1/11/2002 -0500, Matt Pobursky wrote: However, you can request a demo CD of Protel 99SE from Altium and that can be used to view your files. It will be a limited function version (I'm not sure of the limitations though). It can be used, but only for 30 days. This is less than satisfactory. It is *not*, however, limited in function, it is full-function. It's a product demo, not a viewer. For PCB, I recommend generating the gerber and suggesting that the customer use one of the many free gerber viewers. They can even use CAMtastic, and you could send them a CAMtastic file instead of gerbers. A good viewer would be better though, especially if it allowed examination of net attributes. Protel should make the demo default to a viewer after 30 days, thus serving multiple purposes. In fact, I'd recommend that the demo install as a viewer; at any time the user could convert it to full-function, which would then expire in 30 days. This would allow a company to use it as a demo for quite some time and *then* decide to seriously consider purchase, with no complications. It is sufficient to restrict certain kinds of file writing and output, there is no need to make the expired demo *useless*. For schematic, yes, Acrobat. I got a copy of pdfwriter with my digital camera [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic lib ?
I would concur with exactly what Peter has stated. Do two schematic symbols as close to identical for pin locations as is possible. Quite often on a BGA packaged part, there may be a few additional pins used anyway (additional gnds or pwrs, right)? Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. #300 - 4401 Still Creek Drive, Burnaby, B.C., Canada, V5C 6G9. Tel (604) 292-9089 (direct line) Fax (604) 292-9010 Website: www.norsat.com -Original Message- From: Peter W. Richards [mailto:[EMAIL PROTECTED]] Sent: Tuesday, January 08, 2002 11:11 AM To: Protel EDA Forum Subject: Re: [PEDA] schematic lib ? I'd bite the bullet and do this the obvious, hard way: make a standard-numbered BGA footprint (A1,A2...) which you can reuse someday for a different part in the same package, then make 2 schematic symbols, one for each pkg. I'd at least put corresponding pins in the same locs on the 2 symbols so they can be easily 'swapped' in the schematic if necessary... good luck -- Peter W. Richards / [EMAIL PROTECTED] Senior Design Engineer Reflectivity, Inc. ph 408 970 8881 x113 fx 408 970 8840 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic lib ?
I had to organize my sch-lib for the same fact. It is possible to add more than one footprint to each schematic component, but I woudn't do that, because some parts have different numbering for different footprints. ( And perhaps some pins more or less which have to be treated in different ways. ) So the most simple and consequent way is to have a different schematic component for each different package and name it so. ( 74HC00_SO, 74HC00_DIL, 16V8_PLCC ) Georg I was afraid I was going to have to do this. Our engineers have selected a hand full of components that they are going to be using on all of our new designs. All the components picked come in three or four different package formats, which depending on the design are going to be used one time or another. So now I have to flag each component for each foot print. Thank you for the input, Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic driven PCB Layout (and schematic net classes)
Hi Steve! Please beware that when you use PcbDirectives *all* items mentioned in the PcbDirective-menu are placed upon the net. This includes f.e. the 'routing layer' resulting in that the net is*only* routed on that layer as only one layer can be selected. Of course you can delete all the unused design-rules in PCB, but if you use this a lot this becomes a cumbersome task. Especially as only one design-rule can be deleted at a time. You have already discovered that only integers can be entered and that the unit vcan not be entered in the schematic. It is these silly facts that keep me from using PcbDirectives as they are presently available in Protel. I am however in the proces of writing a server that allows the use of the 'width' part of the PcbDirectives as well as add netclasses in the schematic. The latter are similar to the netclasses in PCB, and allow nets to be placed in classes, have directives added to them (Ok, presently only the 'routing width') and transfer those classes to PCB's netclasses. In this process I can also import the 'width'-part of PcbDirectives allowing the user to select the unit (mils, mm or 0.1mm). The MinWidth, Maxwidth and PreferredWidth parameters are stored in the database. I find this way quite usable (although it is not perfect yet). If any of you are interested I can make a slightly more userfriendly version available to the forum. Just let me know. Cheers, Jan Martin Wagenaar [EMAIL PROTECTED] 27-11-01 19:57:17 I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic driven PCB Layout
Yes, so I've reverted to changing the PCB editor to Imperial (using Q shortcut key) before I update from the schematic. I can then set, say 20 (mil) for a track of about 0.5mm, etc.. I then have to change back to metric, but this is a bit long winded, as I have to do a conversion everytime. Steve -Original Message- From: Anthony Whitesell [mailto:[EMAIL PROTECTED]] Sent: 27 November 2001 18:49 To: Protel EDA Forum Subject: Re: [PEDA] Schematic driven PCB Layout Steve, It appears that you have found the quirk called you can only use whole numbers. I tried setting an imperial track with to a decimal and it does not accept it. Protel also does not seem to accept any track width containing a decimal value (ie. 0.5mm, 7.5mm, 0.5mil, or 7.5mil). Does this seem to be the problem? Anthony Whitesell Sunrise Labs 603-644-4500 mailto:[EMAIL PROTECTED] I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic driven PCB Layout
I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic driven PCB Layout
Still playing with this, I discovered that it works if your PCB is set to imperial, but not metric. It seems that the schematic editor can only use imperial measurements..well it seems like that to me. Anyone know how to change this, as I generally use metric!! Steve I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Bug?
Re: [PEDA] Schematic Bug?
Also, I didn't explain why it doesn't work as you explained. I don't know programming wise why, but unless you actually tell protel exactly what you want to change (match attributes section), and what you want it to change to (copy attributes section), protel will tell you that it is going to change 16 parts, because you told it which 16 parts by checking the selection box, but it doesn't know what to change it to. I think this was changed in SP6, because Global Edit could be quite dangerous before, if you accidentally gave protel the wrong information. -Original Message- From: Stephen Smith [mailto:[EMAIL PROTECTED]] Sent: 13 November 2001 19:00 To: Protel EDA Forum Subject: Re: [PEDA] Schematic Bug? I discovered this, but the global edit just takes a bit more tweaking. You have to enter what you want to change on the global menu. For example, if you selected 2 parts, and you wanted to change part type from 1K to 2K, open global menu, select same on selection under attributed to match by and enter 2K in part type box under copy attributes. Also, if you want to change a specific parts lib ref you would have to enter the old lib ref under match by, and new lib ref under copy. Steve -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: 13 November 2001 18:47 To: Protel EDA Forum Subject: [PEDA] Schematic Bug? Hi all, I just recently changed over to SP6 running on Win2K professional. I tried to global edit a schematic part using the selection as the common feature. The customary screen saying I was about to change 16 parts OK? yet when I clicked yes, nothing changed. Has anyone else experienced this? Is this old news and I have just had my head in the clouds? Regards, ...OLE_Obj... GE Energy Services __ Lloyd Good Development Digitization Substation Automation Solutions GE Harris Energy Control Systems Canada, Inc. 2728 Hopewell Place N.E., Calgary, Alberta T1Y 7J7 CANADA Tel: 403.214.4777, Dialcomm: 8.498.4777, Fax: 403.287.7946 Website: www.gepower.com/geharrisenergy/ NOTICE: The information contained in this e-mail is privileged, confidential and intended solely for the use of the addressee named above. If the reader of this e-mail is not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this e-mail is strictly prohibited. If you have received this e-mail in error, please notify me immediately by telephone (collect) at (1) 403.214.4400 and destroy this e-mail as well as any copy. Thank you. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Bug?
[EMAIL PROTECTED] wrote:
Hi all,
I just recently changed over to SP6 running on Win2K professional. I tried
to global edit a schematic part using the selection as the common feature.
The customary screen saying I was about to change 16 parts OK? yet when I
clicked yes, nothing changed. Has anyone else experienced this? Is this old
news and I have just had my head in the clouds?
There are a bunch of things that you need to do to get a global edit to
work on parts. One is that you need to set 'Change ALL Primitives'
from the long bar at the lower right in the global edit box. If you leave
it at 'Change FREE Primitives', it will not affect components (parts)
but only other items on the sheet (lines, net labels, etc.). That is most
likely what happened. There are other settings (selected, footprint,
type, descriptor, etc.) that can prevent a global edit from 'taking'.
But, I think it would be the free/all primitives that would cause it to show
the number of objects to be changed, and then change none of them.
One other possible cause is text string substitution. let's say you select
some parts, and then in the part type field you entered {abc=def} but
no part types in selected components had the string abc in them.
You would also see the number of objects to be changed equal to the
number selected, but nothing would be changed, due to no string
matching the pattern abc.
Jon
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Re: [PEDA] Schematic Bug?
Jon, you're confusing PCB global edit with Schematic (what the thread is about). -Original Message- From: [EMAIL PROTECTED] Sent: Tuesday, November 13, 2001 12:27 PM There are a bunch of things that you need to do to get a global edit to work on parts. One is that you need to set 'Change ALL Primitives' from the long bar at the lower right in the global edit box. If you leave it at 'Change FREE Primitives', it will not affect components (parts) snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Bug?
Dwight wrote: Jon, you're confusing PCB global edit with Schematic (what the thread is about). Probably so. It all sort of blends into one another when I don't have it on the screen in front of me at the moment. But, other than the free/all listbox, I think everthing ELSE I said was mostly correct. Apparently there is a difference in the way global edits work in SP6. Since I have not had any trouble running with SP5, I have stayed there for the moment. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Bug?
This has already been explained by Mr. Elson, but to say it perhaps another way: The message about the number of primitives to be changed tells you how many matches you got. It is a tad different in Schematic than in PCB. PCB does not include the object being edited in the match count, as I recall Schematic does. Further, in PCB, most changes are made directly to the primitive fields instead of in the change field, global changes are transferred if Change or Copy to All -- I forget the exact words -- for that field is checked. So if you get a message saying that 20 objects are going to be changed, you know that you got 20 matches. You do not know that any of them, or more of them than 1, are going to be changed, that depends on the settings in the fields to be globalized. Schematic global edit can drive one a little buggy until one understands it. It took me some time, and I'm still not sure that I've got it all. String-substitution operators are used, there is some information on it in the manual or tutorial as I recall. There are also some irritating limitations, as have been discussed before on this list. The reported behavior is quite common, and it is not a bug, just a tool not being used as designed. Probably. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] schematic port references
I am having difficulties controlling the placement of the port references, mainly they are overlapping the port name which defeates the purpose of having them there. Note this is only in the printing of the schematic though. I was wondering if this had something to do with the scaling of the printout (I am printing an A2 drawing onto an A3 sheet) Yes, I have the right printer driver. Win 2000, SP6. If anybody has had simmilar problems, I would really appreciate any ideas Wayne Bickers Electronic Engineer Tru-Test Limited * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic port references
I too had several problems with incorrect printing (especially overbars on pinnames). Since I checked the Display Printer Fonts box in the Tools-Preferences-Graphical Editing Tab and changed Intercharacter spacing to 6 and Character Width Scale to 100% in the Setup Printer Dialog I get correct Printouts. But this only is true when the printed sheet is opened in the design explorer. Printing a whole hierarchy from the top level sheet as the only opened sheet does lead to the same mess as without these settings for all closed sheets. Don't ask me why and how I found these settings! I just accept it and am happy to get correct printouts this way. Emanuel Wayne Bickers wrote: I am having difficulties controlling the placement of the port references, mainly they are overlapping the port name which defeates the purpose of having them there. Note this is only in the printing of the schematic though. I was wondering if this had something to do with the scaling of the printout (I am printing an A2 drawing onto an A3 sheet) Yes, I have the right printer driver. Win 2000, SP6. If anybody has had simmilar problems, I would really appreciate any ideas Wayne Bickers Electronic Engineer Tru-Test Limited -- MPL AG www.mpl.ch Emanuel Zimmermann [EMAIL PROTECTED] Manager RD Phone: +41 (0)56 483 34 34 Taefernstrasse 20 Fax: +41 (0)56 493 30 20 CH-5405 Daettwil * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
I've seen a mechanism for achieving this recently on another tool. You can add run-time attributes to each gate such as GROUP=FPGA1 and then during annotation only parts with compatible attributes can/will be put together. This could also be very useful for defining components in isolated regions ie. REGION=ISOLATED 5V or some such. I'm not sure, but I think that the Protel database structure should be able to handle another field(s) - perhaps there's a DDB expert who could comment... Doug From: Edi Im Hof [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: Re: [PEDA] Schematic hetero capabilities? Date: Tue, 23 Oct 2001 23:02:28 +0200 At 13:42 23.10.01 -0700, you wrote: The problem I ran into is designator annotation when different kind of graphic multi-part component is made. Protel can not identify which parts are belong to the same component. It will go U1A, U1B...then U2A, U2B...Sometime it brings in the wrong part. Any work around? Thanks. Workaround yes, solution no. Workaround: Annotate those critical parts manualy. This problem araises with all multipart components, Protel should provide the ability to to define with parts belong together. Edi Susan Quintron Systems, Inc. -Original Message- From: Peter Bennett [mailto:[EMAIL PROTECTED]] Sent: Tuesday, October 23, 2001 1:18 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic hetero capabilities? Cliff Ober wrote: I'm working with some large devices (500 pins), and I'm interested in representing the schematic symbols as hetero type devices (split representations of the parts into logical blocks). Is there any efficient way to do this in '99SE? I don't seem to find any references to this in the help or user guide; can anyone suggest a good methodology for accomplishing this? You simply make a multi-part component, the same way you would make the individual gates of a 7400. The different parts of a multi-part component don't need to have the same graphics. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html _ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
Hello all, Wednesday, October 24, 2001 12:58 PM Douglas McDonald wrote: I've seen a mechanism for achieving this recently on another tool. You can add run-time attributes to each gate such as GROUP=FPGA1 and then during annotation only parts with compatible attributes can/will be put together. This could also be very useful for defining components in isolated regions ie. REGION=ISOLATED 5V or some such. I'm not sure, but I think that the Protel database structure should be able to handle another field(s) - perhaps there's a DDB expert who could comment... I think it is already in Protel, look in the 'handbookp99se.pdf' at page 142. You can find the file at www.protel.com. The pagenumber might be different if Protel/Altium updated the file. Look for the subject 'Preparing the Design for PCB Layout, Grouping parts into the same physical component'. Aalt Lokhorst (e-mail [EMAIL PROTECTED]) address: Schut Geometrische Meettechniek bv Duinkerkenstraat 21 9723 BN Groningen, The Netherlands tel. +31 50-5877877 fax. +31 50-5877899 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
Thanks everyone for the help on this; Aalt's pointer to the info about grouping the parts is the key that should allow me to do what I want! Cliff Ober -Original Message- From: Aalt Lokhorst [mailto:[EMAIL PROTECTED]] Sent: Wednesday, October 24, 2001 7:20 AM To: Protel EDA Forum Subject: Re: [PEDA] Schematic hetero capabilities? Hello all, Wednesday, October 24, 2001 12:58 PM Douglas McDonald wrote: I've seen a mechanism for achieving this recently on another tool. You can add run-time attributes to each gate such as GROUP=FPGA1 and then during annotation only parts with compatible attributes can/will be put together. This could also be very useful for defining components in isolated regions ie. REGION=ISOLATED 5V or some such. I'm not sure, but I think that the Protel database structure should be able to handle another field(s) - perhaps there's a DDB expert who could comment... I think it is already in Protel, look in the 'handbookp99se.pdf' at page 142. You can find the file at www.protel.com. The pagenumber might be different if Protel/Altium updated the file. Look for the subject 'Preparing the Design for PCB Layout, Grouping parts into the same physical component'. Aalt Lokhorst (e-mail [EMAIL PROTECTED]) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic hetero capabilities?
I'm working with some large devices (500 pins), and I'm interested in representing the schematic symbols as hetero type devices (split representations of the parts into logical blocks). Is there any efficient way to do this in '99SE? I don't seem to find any references to this in the help or user guide; can anyone suggest a good methodology for accomplishing this? Thanks! Cliff Ober * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
Cliff Ober wrote: I'm working with some large devices (500 pins), and I'm interested in representing the schematic symbols as hetero type devices (split representations of the parts into logical blocks). Is there any efficient way to do this in '99SE? I don't seem to find any references to this in the help or user guide; can anyone suggest a good methodology for accomplishing this? You simply make a multi-part component, the same way you would make the individual gates of a 7400. The different parts of a multi-part component don't need to have the same graphics. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
The problem I ran into is designator annotation when different kind of graphic multi-part component is made. Protel can not identify which parts are belong to the same component. It will go U1A, U1B...then U2A, U2B...Sometime it brings in the wrong part. Any work around? Thanks. Susan Quintron Systems, Inc. -Original Message- From: Peter Bennett [mailto:[EMAIL PROTECTED]] Sent: Tuesday, October 23, 2001 1:18 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic hetero capabilities? Cliff Ober wrote: I'm working with some large devices (500 pins), and I'm interested in representing the schematic symbols as hetero type devices (split representations of the parts into logical blocks). Is there any efficient way to do this in '99SE? I don't seem to find any references to this in the help or user guide; can anyone suggest a good methodology for accomplishing this? You simply make a multi-part component, the same way you would make the individual gates of a 7400. The different parts of a multi-part component don't need to have the same graphics. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
At 13:42 23.10.01 -0700, you wrote: The problem I ran into is designator annotation when different kind of graphic multi-part component is made. Protel can not identify which parts are belong to the same component. It will go U1A, U1B...then U2A, U2B...Sometime it brings in the wrong part. Any work around? Thanks. Workaround yes, solution no. Workaround: Annotate those critical parts manualy. This problem araises with all multipart components, Protel should provide the ability to to define with parts belong together. Edi Susan Quintron Systems, Inc. -Original Message- From: Peter Bennett [mailto:[EMAIL PROTECTED]] Sent: Tuesday, October 23, 2001 1:18 PM To: Protel EDA Forum Subject: Re: [PEDA] Schematic hetero capabilities? Cliff Ober wrote: I'm working with some large devices (500 pins), and I'm interested in representing the schematic symbols as hetero type devices (split representations of the parts into logical blocks). Is there any efficient way to do this in '99SE? I don't seem to find any references to this in the help or user guide; can anyone suggest a good methodology for accomplishing this? You simply make a multi-part component, the same way you would make the individual gates of a 7400. The different parts of a multi-part component don't need to have the same graphics. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic hetero capabilities?
There certainly is Cliff,
I have done this many times. Just create your symbol as with multiple parts
('add a part'in the library editor)like you would for multiple gates or
op-amp packages. When you place the parts on your schematic, pre-assign them
with designators so that an annotation pass (of all '?' designators)will not
swap them around. Back annotation from a re-annotated board will not cause
any problems.
regards,
Phil.
-Original Message-
From: Cliff Ober [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 24 October 2001 4:12 AM
To: Protel EDA Forum
Subject: [PEDA] Schematic hetero capabilities?
I'm working with some large devices (500 pins), and I'm interested in
representing the schematic symbols as hetero type devices (split
representations of the parts into logical blocks). Is there any efficient
way to do this in '99SE? I don't seem to find any references to this in the
help or user guide; can anyone suggest a good methodology for accomplishing
this?
Thanks!
Cliff Ober
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Re: [PEDA] Schematic library object selection question
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** I add my vote for NEVER anything selected when picking from libraries in Schem or pcb. All the same inconvenient hassles here as others have described. Jim Parr. - Original Message - From: Dwight Harm [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, 30 September 2001 09:02 Subject: Re: [PEDA] Schematic library object selection question I also vote for NOT saving the 'selection' state in either PCB-lib or SCH-lib editors. Dwight Harm Trax Softworks, Inc. -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Saturday, September 29, 2001 6:25 AM On 03:42 PM 9/28/2001 -0700, Abd ul-Rahman Lomax wrote: snip It would be better to clear the selections in the saving, I'd vote. If one or the other, I agree. My vote is for automatic de-selection. Any other me-tooers? (If we get ten or more, I'll dump the lot in Protel's mailbox... snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic library object selection question
Without questionde-selection Gene Silvernail - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, October 01, 2001 4:31 AM Subject: Re: [PEDA] Schematic library object selection question On 09:25 AM 29/09/2001 -0400, Andrew J Jenkins said: It would be better to clear the selections in the saving, I'd vote. If one or the other, I agree. My vote is for automatic de-selection. Any other me-tooers? (If we get ten or more, I'll dump the lot in Protel's mailbox as a reminder of the wishes of its constituency. The more, the better) Yep - de-selection for me. And I would go further: I can only see pain (and have only experienced pain) if the symbols/footprints have selected items in them. So I would say the selection status should be forced off when saving. Fullstop. Even if it is a break from the past. Note to those implementing auto-de-selection - I do not wish that a save during a complex library operation should clear the selection status of entities in RAM. Simply it should be forced off in the disk copy. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic library object selection question
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** De-selection! Fred A Rupinski - Original Message - From: Gene Silvernail [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, October 01, 2001 1:34 PM Subject: Re: [PEDA] Schematic library object selection question Without questionde-selection Gene Silvernail - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, October 01, 2001 4:31 AM Subject: Re: [PEDA] Schematic library object selection question On 09:25 AM 29/09/2001 -0400, Andrew J Jenkins said: It would be better to clear the selections in the saving, I'd vote. If one or the other, I agree. My vote is for automatic de-selection. Any other me-tooers? (If we get ten or more, I'll dump the lot in Protel's mailbox as a reminder of the wishes of its constituency. The more, the better) Yep - de-selection for me. And I would go further: I can only see pain (and have only experienced pain) if the symbols/footprints have selected items in them. So I would say the selection status should be forced off when saving. Fullstop. Even if it is a break from the past. Note to those implementing auto-de-selection - I do not wish that a save during a complex library operation should clear the selection status of entities in RAM. Simply it should be forced off in the disk copy. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Diode to PCB errors
Re: [PEDA] Schematic Diode to PCB errors
Eric, I actually have free time for once, so I thought I might answer your question :) You have already discovered the solution to the problem. Let me confirm the problem does in fact lie where you suspect :) ERRORS: 2 macros can not be executed: - Macro 1: New Node Add node D1-1 to net NetR1_1 Error: Node not found Note that the Diode in your schematic library has 2 terminals noted 1 (D1-1), and 2 (D1-2), but your footprint has the terminals noted A and K. This is why Protel can't find the nodes; they do have to match. ...or does the default Protel PCB library have a mistake on every diode, LED and bridge? Yes, to make a long story short, the libraries don't match. You will have to either change the footprints to 1 and 2, or you will have to change the schematic symbol to have pins A and K. Take your pick. This should be pretty embarrassing for Protel at this late date, but they are nevertheless still distributing the libraries this way. Hope this helps, Frank At 04:27 PM 4/3/2001 -0600, you wrote: I've been having minor errors doing a schematic to PCB update while using diodes, LEDs and bridges. For some reason I always get errors such as: ERRORS: 2 macros can not be executed: - Macro 1: New Node Add node D1-1 to net NetR1_1 Error: Node not found Macro 2: New Node Add node D1-2 to net NetD1_2 Error: Node not found Using the default Protel libraries (sch: Miscellaneous Devices.lib and pcb: Miscellaneous.lib) will not work. The syncronizer appears to not like using A or K in the schematic diode pin name and the PCB pad designator. The only way I can get it to work is to change A and K to 1 and 2 on the PCB library part. I would prefer to use the more descriptive names (A , K , AC1 , AC2 etc.) Is there a way to make this work or does the default Protel PCB library have a mistake on every diode, LED and bridge? Thanks, Eric Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Diode to PCB errors
Have you checked that the schematic symbol for the diode you are using actually labels the diodes pins 'A' and 'K' it appears to be using '1' and '2'. -Original Message- From: Eric Albach [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 4 April 2001 8:32 AM To: Protel EDA Forum Subject: [PEDA] Schematic Diode to PCB errors I've been having minor errors doing a schematic to PCB update while using diodes, LEDs and bridges. For some reason I always get errors such as: ERRORS: 2 macros can not be executed: - Macro 1: New Node Add node D1-1 to net NetR1_1 Error: Node not found Macro 2: New Node Add node D1-2 to net NetD1_2 Error: Node not found Using the default Protel libraries (sch: Miscellaneous Devices.lib and pcb: Miscellaneous.lib) will not work. The syncronizer appears to not like using A or K in the schematic diode pin name and the PCB pad designator. The only way I can get it to work is to change A and K to 1 and 2 on the PCB library part. I would prefer to use the more descriptive names (A , K , AC1 , AC2 etc.) Is there a way to make this work or does the default Protel PCB library have a mistake on every diode, LED and bridge? Thanks, Eric * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Diode to PCB errors
It is a discrepancy between the sch and PCB library. Instead of changing the PCB you can change the pin *number* (not name) in the sch symbol. Protel uses sch pin number to match to PCB component pad designator. Pin numbers and pad designators do not need to be numbers they can be alpha-numeric but keep then 4 letters/numbers or less. The pad designator must precisely match the pin number. You can do what you wish (A , K , AC1 , AC2 etc.) but you will need to edit sch library parts as you use them. Copy the parts you use out of the Protel-supplied libraries and build up your own set of libraries. You will rapidly get to a point where you are only creating a new symbol/footprint occasionally. (I use A/K, C/E/B, D/G/S, etc for my sch symbols pin numbers.) Ian Wilson On 04:27 PM 3/04/2001 -0600, Eric Albach said: I've been having minor errors doing a schematic to PCB update while using diodes, LEDs and bridges. For some reason I always get errors such as: ERRORS: 2 macros can not be executed: - Macro 1: New Node Add node D1-1 to net NetR1_1 Error: Node not found Macro 2: New Node Add node D1-2 to net NetD1_2 Error: Node not found Using the default Protel libraries (sch: Miscellaneous Devices.lib and pcb: Miscellaneous.lib) will not work. The syncronizer appears to not like using A or K in the schematic diode pin name and the PCB pad designator. The only way I can get it to work is to change A and K to 1 and 2 on the PCB library part. I would prefer to use the more descriptive names (A , K , AC1 , AC2 etc.) Is there a way to make this work or does the default Protel PCB library have a mistake on every diode, LED and bridge? Thanks, Eric * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Diode to PCB errors
Re: [PEDA] schematic on my PCB ??
thanks everybody! that took care of it... unchecking the generate boxes at the bottom of the update pcb process didn't quite finish the process. i believe it would have been enough if i hadn't gotten myself dirty by heading down the wrong path in the first place. i had to also do what peter suggested, and go into design rules and get rid of the room definitions. thanks again, miker -Original Message- From: Peter Bennett [SMTP:[EMAIL PROTECTED]] Sent: Friday, April 06, 2001 11:16 AM To: Protel EDA Forum Subject: Re: [PEDA] schematic on my PCB ?? Robison Michael R CNIN wrote: hello, i changed some things around on a multipage schematic for a previously built board, and now for some reason or other after i updated the pcb, i have red crosshatched squares on my pcb file that correspond to the pages of the schematic. Those are the idiotic rooms that are supposed to be an aid to parts placement. i've tried refreshing the window and shutting it down and restarting it but they persist. i believe that i've inadvertently selected some option to do this but i don't know what it was and i'd like to get it off my pcb view. could someone please tell me what i've done and how to undo it? In Schematic, do Update PCB, and be _sure_ to uncheck Generate component classes for schematic sheets at the bottom of the form. Also, in PCB, go to Design Rules/Placement and remove any entries under Room Definition. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] schematic on my PCB ??
hello, i changed some things around on a multipage schematic for a previously built board, and now for some reason or other after i updated the pcb, i have red crosshatched squares on my pcb file that correspond to the pages of the schematic. i've tried refreshing the window and shutting it down and restarting it but they persist. i believe that i've inadvertently selected some option to do this but i don't know what it was and i'd like to get it off my pcb view. could someone please tell me what i've done and how to undo it? thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic on my PCB ??
I got tired of always having to uncheck the box, so I just leave them, but make them hidden -- rt-click, Options, Show/Hide, Rooms. BTW, the Add component class macros should have been in the Update Design list when Mr. Robison synchronized -- I always review the list to make sure it's doing what I expect. Dwight. -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED]] Sent: Friday, April 06, 2001 11:49 AM Robison Michael R CNIN wrote: hello, i changed some things around on a multipage schematic for a previously built board, and now for some reason or other after i updated the pcb, i have red crosshatched squares on my pcb file that correspond to the pages of the schematic. i've tried refreshing the window and shutting it down and restarting it but they persist. i believe that i've inadvertently selected some option to do this but i don't know what it was and i'd like to get it off my pcb view. These are rooms, that are useful in controlling pre-placement of parts, but aren't much use after that. Simply click on them and hit shift/delete. I have no use for them, myself. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic on my PCB ??
At 09:07 AM 4/6/01 -0700, Peter Bennett wrote: Those are the idiotic rooms that are supposed to be an aid to parts placement. As I recall, we are the idiots who asked for this feature. Just because one does not need the feature in one's own work doesn't mean that it is useless. The room concept is broader than the aid-to-parts-placement purpose, but, for now, it is great that there is a tool which can be used to automatically place parts in blocks according to schematic page. Schematics, especially well-drawn ones, quite frequently are organized in such a way that associating the parts on them is very helpful in placement. This is why we asked for this tool. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic on my PCB ??
When you select Update PCB in the schematic editor, a dialog appears which has a checkbox at the bottom labeled: Generate component class for all schematic sheets in project Uncheck that to prevent the generation of placement rooms. John Williams QualECAD Robison Michael R CNIN wrote: i changed some things around on a multipage schematic for a previously built board, and now for some reason or other after i updated the pcb, i have red crosshatched squares on my pcb file that correspond to the pages of the schematic. i've tried refreshing the window and shutting it down and restarting it but they persist. i believe that i've inadvertently selected some option to do this but i don't know what it was and i'd like to get it off my pcb view. could someone please tell me what i've done and how to undo it? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic now rooms
Hello All I find using rooms especially helpful for poorly drawn schematics. Many designers I work with today will place 5 or six components bearing one function together on page one and though these parts may tie into a functional block on page 11, it difficult to decipher how a poorly drawn schematic will flow. Unlike groups, I have the flexibility to move parts more freely, however I wish I could place a room and all of the components inside the room would automatically be placed into a component class. I have also used the rooms for illustration purposes when I had to conduct floor planning reviews. I label the rooms using the engineers functional name and his electrical flow is very intelligible for a design review. But what do I know I'm just another idiot asking for more idiotic features. Mike Reagan EDSI Frederick MD Abd ul-Rahman Lomax [EMAIL PROTECTED] on 09.04.2001 04:59:22 Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc: Subject: Re: [PEDA] schematic on my PCB ?? At 09:07 AM 4/6/01 -0700, Peter Bennett wrote: Those are the idiotic rooms that are supposed to be an aid to parts placement. As I recall, we are the idiots who asked for this feature. Just because one does not need the feature in one's own work doesn't mean that it is useless. The room concept is broader than the aid-to-parts-placement purpose, but, for now, it is great that there is a tool which can be used to automatically place parts in blocks according to schematic page. Schematics, especially well-drawn ones, quite frequently are organized in such a way that associating the parts on them is very helpful in placement. This is why we asked for this tool. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 Dear Mr. Lomax, thank you for your explanation of the intention of this feature. I too was wondering what this was supposed to be good for, as it only messes up my PCBs if I don`t uncheck the box in update PCB. I can well understand that some circuits, especially analogue ones with lots of discrete components, can make good use of this feature if drawn in the way you describe. Possibly Mr. Bennett does designs like I do, with a number of IC's with high pin count or several different gates, which cannot be placed on one sheet of the schematic, if you want to keep it readable. I, for instance, devide high pin count components into different function parts in the library (e.g. 1st part PCI bus interface, 2nd part local bus interface, 3rd part control/port/or other signals, 4th part power supply pins). This is a handy way of building functional blocks within a schematic, but, as different parts of the components are placed on different sheets of the schematic, the rooms feature makes no sense any more for this kind of design. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic now rooms
Mr. Lomax Thank You, Thank You, Thank You! Mike Reagan EDSI At 07:45 AM 4/9/01 -0400, Mike Reagan wrote: however I wish I could place a room and all of the components inside the room would automatically be placed into a component class. I have also used the rooms for illustration purposes when I had to conduct floor planning reviews. I label the rooms using the engineers functional name and his electrical flow is very intelligible for a design review. But what do I know I'm just another idiot asking for more idiotic features. Not. Select the components one desires to associate with a room. Design/Classes/Component/Add/Class_Generator/Selection/True and create a class of the selected components. Then assign that class to the room. Not exactly one-button, but close. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic library tips
Re: [PEDA] schematic library tips
David, see my comments interspersed below. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: David Cary [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 25, 2001 8:54 AM To: [EMAIL PROTECTED] Subject: [PEDA] schematic library tips Dear Protel users, I'm trying to use a 176 pin component. Is there a way to list all the pins and whether each one is input, output, etc. ? It's a real drag double-clicking each one, comparing its electrical type to my data sheets. Was already mentioned, use the report facility within the library editor. It's obvious on symbols with a common geometric representation (NOR gates, inverters). On larger chips, the pins marked with the little triangle CLK symbol are obviously inputs, but what about the other (non-clock) inputs and outputs ? There is no standard per se, somebody probably has some methodology but it is probably in conflict with other standards. symbols, a power part and 4 identical function parts. One must remember to place *all* the parts of a real component somewhere on the schematic. I don't quite understand your comment here, there is no absolute requirement to place all parts. It is much cleaner in a number of ways which include, all parts are on the sheet, all inputs/outputs can be properly terminated. Is there a standard way to indicate (on paper) which pins are input and which pins are output on a (b)-flavored schematic symbol ? No. Does anyone actually use the Hi-Z pin type ? I use all the proper pin types. It does generate a fair number of error/warning reports but then that just makes me double check everything to assure the design is as intended. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic Report
At 10:54 AM 4/18/01 +0200, Juergen Paape wrote: Hello User, who can tell me , how I can get the * component count * pin count * net count report from a (hirarchical) sheet (Protel99SE (SP6))? For me as a member of a design service company is it important to know this for my calculation. Here is how I would do it, off the top of my head: (1) generate a type 1 net list (the old Protel format). Load it into a word processor. (2) separate the list into two lists, the part section and the net section. Eliminate any comment sections. (3) in the part section search and replace close-bracket/return (in Word, ]^p) to something like @. (4) edit the remaining returns to tabs (^p - ^t) (5) do the same with the net section, only use close-paren/return. (6) load each list into a spreadsheet like Excel, as a tab-delimited database, no header row. You might be able to use the Protel spreadsheet, but I'm not promising that The record count in the database is the number of parts or nets, respectively. As to pin count, you can assign pin counts to each component in the spreadsheet and calculate the total number of pins. More importantly, in fact, you can assign areas to each component footprint and calculate density. I wrote utilities to partially automate this process. One could assign fields to each symbol with pin count and footprint area, which presumes that only one footprint is being used for the symbol. In that case, one should be able to use the spreadsheet editor to calculate all the needed values. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] schematic library tips
Dear Protel users, I'm trying to use a 176 pin component. Is there a way to list all the pins and whether each one is input, output, etc. ? It's a real drag double-clicking each one, comparing its electrical type to my data sheets. It's obvious on symbols with a common geometric representation (NOR gates, inverters). On larger chips, the pins marked with the little triangle CLK symbol are obviously inputs, but what about the other (non-clock) inputs and outputs ? There seem to be 2 main schematic symbol types: (a) functional: a symbol has inputs on the left (and sometimes top and bottom), outputs on the right. The power symbol for a component has positive power on top, ground and negative power on bottom. Common for discrete gates (AND, NAND, NOR, etc.) and op amps. Some libraries break a quad package into 5 symbols, a power part and 4 identical function parts. One must remember to place *all* the parts of a real component somewhere on the schematic. (b) pseudo-layout: the symbol on the schematic has roughtly the same shape (rectangular or square) as the real, physical component. Each and every the pin on the real, physical component is shown on the symbol in roughtly the same relative position. Is there a standard way to indicate (on paper) which pins are input and which pins are output on a (b)-flavored schematic symbol ? Does anyone actually use the Hi-Z pin type ? -- David Cary schematic design tips: http://groups.yahoo.com/group/protel-users/files/protelfaq.html#symbols * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic library tips
On Wed, 25 Apr 2001 10:54:23 -0500, David Cary wrote: I'm trying to use a 176 pin component. Is there a way to list all the pins and whether each one is input, output, etc. ? It's a real drag double-clicking each one, comparing its electrical type to my data sheets. Library editor Reports | Component gives you a list of pin names/number/type for the current component. Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
