While editing a template you can edit all graphics on it as well, so you can delete
Protel logo if you wanted. You can also delete a special string, which is in your case
file path. The template has to be opened as a .dot file.
Cheers,
Igor
Hi all,
I'm having trouble wrapping my head around
Agree with nVidia, they are working quite well. I used GeForce 440MX 64MB and was more
than happy. Then I changed to Radeon 9600 128MB dual head that was much faster. Both
running without any problems.
Cheers,
Igor
-Original Message-
From: Terry Creer [mailto:[EMAIL PROTECTED]
Sent: Wed
Dennis,
keep your PCB file open, open your PCB library and display the footprint you want to
update. Click on the 'Update PCB'. That should update all your footprints of the same
type.
Cheers,
Igor
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
Sent: Wednesday, 28
Maybe it could be called 'Balanced Copper Coverage' rather then 'Thickness'? Or 'Track
Density'? 'Thickness' is rather ambiguous in this case. My goal is always to take off
as little Copper as possible. It prevents warping and improves EMC performance. It is
good for the environment as well, esp
And add 6/6 in between to smooth the transition.
Are you sure you are joking here? :)
Igor
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
Sent: Wednesday, 21 January 2004 11:48 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Autorouter
$3K for the full version seems qu
Dom,
Go to 'Rules'. In 'Acute Angle Constraint' choose 'Net Class' for 'Filter Kind', then
click on 'Edit Classes' and add a new class. In that class put all nets except nets
connected to your polygons. Then, once back in the rule dialog, choose the net class
you created from 'Net Class'. This
Have you got x and y pad sizes same as the hole size? And untick the 'Plated' box.
Regards,
Igor
-Original Message-
From: Drew Mills [mailto:[EMAIL PROTECTED]
Sent: Thursday, 15 January 2004 2:54 PM
To: 'Protel EDA Forum'
Subject: [PEDA] Gerber output problems
Hi all,
I completed the
Hamid,
Altium is selling P99SE with a free upgrade to DXP. Then you get a free upgrade to
P2004, so you have all three versions for the price of one. I am not trying to bring
Altium sales up, just think that we should be fair to them and state all the facts. If
your customers bought P99SE or DX
You can set the pad size as small as you want, even as a negative value. Usually, I
set it to 0 (zero) to make sure the pad copper does not show at all. If you want to
sort them by size and still don't want copper, set pad sizes to different negative
values.
Dennis, this is not an attempt to gi
Foot in the mouth disease is spreading fast. It seems I caught it, too.
Mike's idea looks so obvious, someone should have come to this earlier. Combine it
with JaMi's idea and it seems to be feasible as an open source project.
Is anyone else sick? Is there an antidote?
Igor
-Original Messa
Rich,
this topic was discussed a while ago. You might have a look into the archive.
Regards,
Igor
-Original Message-
From: Rich Thompson [mailto:[EMAIL PROTECTED]
Sent: Wednesday, 24 September 2003 2:42 AM
To: Protel EDA Forum
Subject: [PEDA] Off topic: Drawing revision control and PLM
Maybe they were not mis-leading us intentionally. They changed their policies a lot
recently, with ATS and DXP and all, so P99SE got a boot, as they could not afford to
support two versions of SW. We might want to follow this path, though, to get SP7. It
seems to be ideallistic cause now, but it
Bill,
we have implemented a Protel library system similar to what you describe. It makes use
of Protel .ddb file access control. In Design Team folder in library .ddb you will
find another foolder, called Members. There you set up names and passwords for all
people with access to the library.
I beleive to have read somewhere that the center is calculated from the component
outline on the Top Overlay. Don't take me for it, it is just from the memory.
Regards,
Igor
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]
Sent: Tuesday, 26 August 2003 1:28 AM
To: Protel E
obert
"Igor Gmitrovic"
<[EMAIL PROTECTED]To: "Protel EDA Forum" <[EMAIL
PROTECTED]>
Adeline,
go to Tools->Annotate(untick Current Sheet Only box)->Advanced Options and set a range
for designators on each sheet in the project. We usually set top level sheet to the
range of 0-99 and then child sheet 1 to 100-199, child sheet 2 to 200-299, second
level child sheet 1 to 1000-1999,
Hi Choong,
upgrade to service pack 6, make sure you have at least 256MB of RAM and a good video
card.
Regards,
Igor
-Original Message-
From: Choong Keat Yian [mailto:[EMAIL PROTECTED]
Sent: Thursday, 17 July 2003 1:10 PM
To: Protel EDA Forum
Subject: [PEDA] Protel 99SE experience
Hi
Raoul,
your problem might be in scaling the printout in the Print Preview. Open your preview,
right click on the top line in the left pane (it's your printer's icon) and change the
scaling.
Regards,
igor
-Original Message-
From: Natalie DeGennaro [mailto:[EMAIL PROTECTED]
Sent: Tuesda
Nathan,
it will only work with Delphi 5.
Igor
-Original Message-
From: Nathan Horsfield [mailto:[EMAIL PROTECTED]
Sent: Monday, 23 June 2003 10:30 AM
To: [EMAIL PROTECTED]; [EMAIL PROTECTED]
Subject: [PEDA] Protel 99 SE SDK
Good Morning All,
Currently trying to create some servers usi
Another corollary is "The grass is brown wherever you go". It might not be the colour
of grass, it might just be a vision problem.
Igor
-Original Message-
From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]
Sent: Friday, 20 June 2003 11:13 PM
To: Protel EDA Forum
Subject: Re: [PEDA]
Sorry for the previous blank post, too fast on the trigger.
Craig,
you could do several things.
1. Create a net class for all your copper tracks and use the class in instead of
(All) your rule.
2. Create a separate rule for each of the copper layers instead of (All).
Those are the f
-Original Message-
From: Craig Wroth [mailto:[EMAIL PROTECTED]
Sent: Friday, 20 June 2003 11:44 AM
To: Protel EDA Forum
Subject: [PEDA] KeepoutLayer & Rules
Hi,
Having problems geting my rout to follow the following rule in DXP,
Processing Rule : Clearance Constraint (Gap=40mil) (All),
I am sure that in the early days of Power Print the option to print a negative of the
.ppc file was there. It was a good feature, shame it's got lost. It should be
introduced back into DXP. If you still have the trial version of the Power Print
somewhere, you might be able to use it, maybe with
Steve,
in whatever M$ OS you choose, I have never had any problems with P99SE SP6, except the
utopian SP7 issue.
Igor
-Original Message-
From: Steve Smith [mailto:[EMAIL PROTECTED]
Sent: Thursday, 12 June 2003 4:29 AM
To: Protel EDA Forum
Subject: [PEDA] 99SE ON WIN XP
Hi,
I have nev
Dennis,
I have the same problem but no solution, unfortunately.
Igor
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
Sent: Thursday, 13 March 2003 9:42 AM
To: Protel EDA Forum
Subject: Re: [PEDA] SORT ORDER IN LEFT PANE
SE99 SP6
i think this was kicked around befo
Leonard,
I just exported .DWG from schematic and imported it into Visio Technical 5.1.
Exported as AutoCAD v13 drawing, metric. Imported as ISO, metric, A3. The drawing
elemnts can't be ungrouped or edited, drawing can be resized, there are no problems
with fonts, it's all one colour. Initially
Ian,
let me try:
Rule Name Scope MinMax
All holes Board 28mil 280mil
Drill 42mil Power Tracks (Net class)42mil 42mil
Drill 35mil Signal Tracks (Net class) 35mil 35mil
Drill 28mil Special
Ian,
you wrote:
>The first rule has the highest priority. Rules are tested against all
>objects. So your first rule will generate an error on all holes not equal
>to 42mil. It won't help that you have alternative rules following.
I would say, that the rules are tested against all objects co
Alexandre,
set the scope to check only the holes of certain size or certain net, not the whole
board.
Igor
-Original Message-
From: Alexandre Desnoyers [mailto:[EMAIL PROTECTED]
Sent: Monday, 24 February 2003 9:50 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] Hole Size Constraint
I want to
I beleive this is one of the parts built into the simulation SW, together with several
other components, e.g. CAP and RES. You can access those by writing your subckt
models. To do this you will have to dig into other parts, to see how it's done. E.g.,
try using SPDTRELAY instead of switch. You
Peter,
to answer your question from below, there is a way to do it.
In a top level schematic place a sheet symbol. On the sheet symbol place a
bidirectional port (e.g. 12V). Connect a wire to that port and connet it to your 12V
rail.
On a sub-circuit place a bidirectional port of the same name
Ian,
try these people
http://www.imppc.com.au/
Igor
-Original Message-
From: Ian Capps [mailto:[EMAIL PROTECTED]]
Sent: Friday, 7 February 2003 1:05 PM
To: Protel EDA Forum
Subject: [PEDA] Aus PCBs
This is OT but I would appreciate some feedback from Australian users on any
Aus manufa
Peter,
I should have read your post with more attention.
It sometimes works, but I don't have time to find out what it is that makes it work.
Usually, I make copies of the channels manually and then annotate. There is another
problem with complex hierarchy, and it is that once you execute 'Comp
Peter,
in Tools->Annotate you can define how to annotate your schematic sheets. Choose to
annotate the whole project and in Advanced Options dialog set the suffixes for each
individual schematic sheet. That will enable you to differentiate between part naming
on individual channels in your desi
Gisbert,
One workaround could be to keep your fanout/prereoute topology separate from the
footprint in a .pcb file and keep your footprint clean of additional primitives. Then,
when you need the footprint you could copy and paste the fanout/prereoute section into
your design. In that way you co
Dave,
may sound trivial, but check your licence setting and make sure the autorouter is
enabled.
Regards
Igor
-Original Message-
From: Sanders, Dave [mailto:[EMAIL PROTECTED]]
Sent: Friday, 6 December 2002 1:43 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Unable to Initialize
Thanks
John,
File sharing feature works fine accross network and shared drives. If two users with
the same access privileges try to open the same file, the second user will be denied
access. The same second user can access other files in the same .ddb if they are not
accessed by the first user. The ad
email: [EMAIL PROTECTED]
http://www.norsat.com
Check out our fall promotion at www.norsat.com. Limited quantities. Sale
ends December 24, 2002.
Contact your Account Manager or call 1-800-NII-4LNB or email
[EMAIL PROTECTED]
> -Original Message-
> From: Igor Gmitrovic [mailto:[EMAIL PROTE
ked, what exactly do you mean?
Hope you have a good one, too.
Regards,
Igor Gmitrovic
R&D Engineer
HPM Industries Pty Ltd
Ph: ++ 61 2 9207 9550
Fax: ++ 61 2 9207 9554
Email: [EMAIL PROTECTED]
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 4 D
Brad, Mike
my understanding of the question is that there are more than four footprints that
could be used for a component. Let's say a capacitor. There are four footprint fields
in the sch component library and there couldb be 53 different footprints one uses for
capacitors. There is obviously
Terry,
you might have some hidden objects in your components. That would explain why Protel
takes time to process it. Or your component may be corrupted in some other way. Try to
select all the visible objects in the component and then copy-paste to a new
component. Then check if it still does
Mike,
at least you would let us know about it and save us some frustration.
Igor
-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Friday, 22 November 2002 1:07 PM
To: Protel EDA Forum
Subject: Re: [PEDA] What else is under the hood
Dennis,
This program sometimes is
Michael,
we use both overlays and several mechanical layers to compile the assembly
information. We assign different mechanical layers for Designators and Comments, as
well as other information, such as dimensions, panellisation and glue stencil pads.
And we use the Protel PCBPrint to print o
Yuriy,
if you reload the netlist and check the "Update Footprints" box it would update all of
them. I know it is not updating from library, as your question asks, but it does the
job.
Igor
-Original Message-
From: Yuriy Khapochkin [mailto:[EMAIL PROTECTED]]
Sent: Saturday, 16 N
Hi Steve,
yes the protel P&P file is usable. We use spreadsheet metric format, so it's easier to
edit the file in Excel. Our origin is set onto one of the fiducial marks. The way you
set the origin is defined by your P&P machine and the way you panellise the board.
There was some discussion rec
Interesting,
a friend of mine working for another company reported the same problem today. The
polygon Plane parameters were setup correctly. We tried to play with the DRC rules. It
was the only polygon on the board. Nothing could be done. Any ideas?
Igor
-Original Message-
From: Brian
The odds seem to be zillion (of us) to one (Altium). The problem with gambling is that
the rules are set by the guy who deals the cards. That also means the rules can be
changed at any time.
Igor
-Original Message-
From: Dennis Saputelli [mailto:dsicon@;integratedcontrolsinc.com]
Sent:
appearing - DXP -> Earlier Version -> DXP
Well if the problems is with a version earlier than DXP, then maybe the
problem is not still there. Maybe it's still with the older versions.
It seems like it would be pretty easy to find, once someone notices it.
> -Original Messag
Brian,
so it is still there. I have seen it in P3, P98 and P99 when importing files from
previous versions of Protel into the latest version. DOS version files were the most
probable to result in zero size pads.
Igor
-Original Message-
From: Brian Watson [mailto:brian@;desktop-eda.com.
sound. IF the problem is a bug in an old
version of Protel, then there is nothing a new version can fix. It's not
the old format that is flawed, it's old data that is getting corrupted.
I don't see what difficult to understand.
Tony
> -Original Message-
> From: Igor Gm
Jon,
if this is true, it then explains why all those short tracks appear under pads.
Basically, it is not a gridless autorouter, unless there is a definition of 'gridless'
that is different from my understanding of the word.
Igor
-Original Message-
From: Jon Elson [mailto:[EMAIL PROTE
JaMi,
there it is, the root of your problems. You have only 128MB of RAM. Upgrade that and
you will have Protel running happily and will save yourself a lot of frustration. And
don't forget to install a video card with at least 16MB RAM. They don't even make them
with less than 32MB today.
Ig
Hugh,
have the logo in .bmp black and white, then convert it to .dwg format and import it
into the blank .pcb. Then create a component and place it into your PCB library. From
there you can import it automatically through the netlist in any of your PCBs.
Cheers,
Igor
-Original Message---
All,
I see there is a lot of diplomacy and politeness being flogged around. So, before we
all get civilised again, let me throw some more oil into the fire.
In my opinion there are legitimate, logical and electrically correct reasons to use
4-way junctions. E.g., if I wanted to represent the s
orientation. I can't remember where it came from (could have been a
commercial website).
TC
-Original Message-
From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 10 October 2002 2:03 PM
To: Protel EDA Forum
Subject: Re: [PEDA] flipping board
Don't even joke a
Don't even joke about it. Shame on you ;)
Igor
-Original Message-
From: Terry Creer [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 10 October 2002 12:46 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] flipping board
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sen
Tony,
that would be one of the ways to create a pick'n place file for bottom layer.
Igor
-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 10 October 2002 9:36 AM
To: 'Protel EDA Forum'; 'Protel Developers Forum'; 'Open Topic Forum'
Subject: Re: [PEDA] f
You could un-group the sch symbols by deleting them from the group in the library.
Each part will then have its own symbol and the update should work.
Igor
-Original Message-
From: Duane Foster [mailto:[EMAIL PROTECTED]]
Sent: Friday, 4 October 2002 4:24 AM
To: 'Protel EDA Forum'
Subjec
Hi Brad,
there were cases when I had to update a pcb two or three times before it completed
correctly. Don't know why it happened. After that the board was done without any
further problems.
Regards,
Igor
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Thursd
ication
> -----Original Message-
> From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, September 19, 2002 6:09 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Unplated pads
>
>
> Just make them Top Layer pads.
>
> Igor
>
* * * * * * * * * *
Or Bottom Layer, depends on your board.
Igor
-Original Message-
From: Igor Gmitrovic
Sent: Friday, 20 September 2002 11:09 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Unplated pads
Just make them Top Layer pads.
Igor
-Original Message-
From: Thomas [mailto:[EMAIL PROTECTED
Just make them Top Layer pads.
Igor
-Original Message-
From: Thomas [mailto:[EMAIL PROTECTED]]
Sent: Friday, 20 September 2002 10:34 AM
To: Protel Data Forum (E-mail)
Subject: [PEDA] Unplated pads
Our board house has asked us to de-check the "Plated" box for single sided
pads.
Ok, 1 gl
JaMi,
Auto Route->Stop works for me. It doesn't do it to my board, either, if pre-routes are
locked. Sorry to bring you the bad news, but you have too many problems with Protel.
Maybe it's time to have a look into some HW/SW compatibility in your PC, or, excuse my
forbidden thoughts, change it
Dave, Ian,
I have seen this behaviuor when importing a pcb from Protel DOS into Protel 3 and
Protel 98. Those happened to be pads with zero diameter and polygons with zero size.
Try to search for those objects in the reports and check if there are any. After
increasing their size I was able to
Let me do it again:
I really want my SP7!
Igor
-Original Message-
From: Brooks,Bill [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 11 September 2002 8:38 AM
To: 'Protel EDA Forum'
Subject: [PEDA] I want my I want my... I want my SP7
:)
Bill Brooks
***
Brian,
I assume you need SMD caps. Have a look at MURATA multilayer ceramic chips, maybe LL
series. For your prototype, I would suggest you solder a cap of 1-2uF directly on top
of the IC, connecting accross power pins and using small multistranded wire. You could
put several of them in paral
tel 99 SE on other systems.
>
> We have no input for Protel 99 on any systems.
>
> We know it happens with Protel 98 in Win98.
>
> We have no input for Protel 98 in Win95 or NT4.
>
> Thanks again,
>
> Let me know if you think of something,
>
> JaMi
>
That's called action. The "nastygrams" are not coming anymore.
Igor
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Monday, 9 September 2002 1:26 PM
To: Protel EDA Forum
Cc: JaMi Smith
Subject: Re: [PEDA] Cease the spam
Bingo!
I think you hit the nail on the head
t I thought that we were heading for a unanimous consensus on
this one.
Thanks for responding.
At least we are building a database of sorts.
JaMi
PS. Maybe we need to have someone make a "Sound Bite" that says "Ah s___!
Protel crashed again!" and set it up for the "Crit
this picture.
Igor,
It does NOT go "KLUNK!" when you exit Protel 99 SE from the "Exit" selection
of the "File" menu pulldown?
Is your "sound" turned on?
What type of machine and what OS are you using?
Thanks,
JaMi
- Original Message -
From: "I
be? A copy of the message is included
below:
>-Original Message-
>From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
>Sent: Monday, 9 September 2002 9:08 AM
>To: Igor Gmitrovic
>Subject: CEASE THE SPAM
>If this waste of our resources does not cease immediately, pleas
There are many factors in the same equation, but as I see it, they had to come up with
something completely new so they could introduce the ATS. That, to me, is the most
important factor in all this. They are fighting for revenue, as any other busines
does. That they might lose in the end is a
In my experience Protel versions 3.0, 98 and 99 were "flaky". Protel 99SE with SP6 is
stable. I aggree with you on SP7. There are things to be corrected.
Igor
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Saturday, 7 September 2002 6:41 PM
To: Protel EDA Forum
Cc:
doesn't do it to me
Igor
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Saturday, 7 September 2002 5:21 AM
To: Protel EDA Forum
Cc: JaMi Smith
Subject: [PEDA] Whats wrong with this picture.
OK . . .
So I'll admit, I missed the Class on Protel 99 SE Basics . . .
you said it all
Igor
-Original Message-
From: Fabian Hartery [mailto:[EMAIL PROTECTED]]
Sent: Saturday, 7 September 2002 1:51 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] DXP - Crunch time?
Dennis,
The only thing I could relate to with demolishing a DDB architecture is that
there is
Maybe it's just window size dragged to the edge. Try increasing the window size by
dragging it to the left.
Igor
-Original Message-
From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
Sent: Friday, 6 September 2002 5:21 AM
To: Protel EDA Forum
Subject: [PEDA] Document manager tree gone in
Barry,
we have tried that as well. In our experience, DXF files are not imported correctly
into Protel (any version). DWG files on the other hand worked fine and we used that
format for both import and export to AutoCAD LT and ProE.FWIW
Igor
-Original Message-
From: Barry, Rick [mailt
Steve,
You could have a pad on the outside and a via inside. That would leave you with one
pad. Pad would have to have its hole diameter larger than the via diameter and should
have to be marked as 'not-to-be-drilled' and not plated. How complicated is that going
to be for your your pcb shop?
Terry,
you know what's best for you. To see what other people are doing, have a look at the
topic 'SV: Hard Look at other Programms'. From what I have seen so far, your thoughts
are in line with a lot of the people in this forum and are definitely in line with
mine.
Cheers,
Igor
-Origin
Jason,
another option could be not to cross hatch the polygons but to do only vertical or
horizontal pouring.
Igor
-Original Message-
From: Jason Morgan [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 27 August 2002 10:22 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] File Size Limit?
Nope,
Malik,
You could decrease the number of undo steps for schematics and pcb editors, in
Tools->Preferences menus. This will free up some of your RAM. You could also consider
adding more RAM. There is a non-linear function between the component count and the
time it takes to DRC a board. For a co
ker tracks =
lower inductance = better immunity... (?)
> -Original Message-
> From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]]
> Sent: Friday, 16 August 2002 11:43 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Matched Lenghth Constraint
>
>
> Danny,
>
> wher
Danny,
wherever you have a change in the inductance, i.e. track width, you will get
reflections. In such conditions yo could get standing waves as well, although I don't
think that working frequencies on your board are so high to be affected by this. Wider
track is equivalent to a broadband an
I would not recommend anyone to use 90deg corners as you will run into the emc
problems.
Igor
-Original Message-
From: Narinder Kumar [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 14 August 2002 9:50 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Matched Lenghth Constraint
Hi Mr. Malik,
1
Hi Kat,
Do Edit->Paste special and tick on Duplicate designators. Tick off Keep Net Name. You
could also do Paste Array.
Igor
-Original Message-
From: Katinka Mills [mailto:[EMAIL PROTECTED]]
Sent: Sunday, 11 August 2002 9:48 PM
To: Protel EDA Forum
Subject: [PEDA] P99SE lockups
Hi a
Ian,
well said. People have tried to hint before that it has gone over the top.
Igor
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 1 August 2002 6:51 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Speaking of Protel Bugs. - Flame start!
On 11:24 PM 31/07/
Matt,
Protel has a bad track in documenting their 'features', but this one is in a Protel
99SE book, page 80, although it is somewhat unclear that the wire is in fact a
polyline. And I am sure it is in previous editions' books as well.
Igor
-Original Message-
From: Matt Pobursky [mail
Vincent,
My two bit(che)s in reply: See inserts
Igor
-Original Message-
From: vincent mail [mailto:[EMAIL PROTECTED]]
Sent: Friday, 2 August 2002 6:42 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Not DXP or P99SE, but have you seen the Cadence
offer! !!!
Darryl Newberry wrote:
>Ah,
Tim,
if you use those holes just for the mechanical fixing points, you can create them by
using Fills in the footprint. If you want to plate them through, there are some PCB
manufacturers doing it on request. If you want to create them as pads, that is not
possible. You will have to wait until
And it looks like beta v2 to me.
Igor
-Original Message-
From: Andrew Jenkins [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 31 July 2002 10:01 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] DXP Discussion
> -Original Message-
> From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
>
So the saga continues. You can bet their sales guys are happy. They have new shiny
interface to sell. Gether all you vain engineers. There are new glass perls and DXP
mirrors in the shop.
Igor
-Original Message-
From: John Ross [mailto:[EMAIL PROTECTED]]
Sent: Monday, 29 July 2002 9:39
Jami,
don't take it personally. This is a discussion forum and not a winner-gets-to-live
arena. We have several Dell machines with identical HW and identical SW. The only
difference are the M$ and Protel licence numbers. Some (in fact only one) have mouse
problems in Protel, some don't. So, wh
Has anyone got 3D models for QualECAD's 3D View other than the sample ones available
from QualECAD?
Igor
* Tracking #: 90D0420EA8562A48BA6FE3E9BBC03868CFDDF957
*
We had no problems with designators on mech layers.
Igor
-Original Message-
From: Steve Wiseman [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 25 July 2002 6:06 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Refdes on other Layers
25/07/2002 06:11:53, "Waldemar Kulajew"
<[EMAIL PROTECTED]> w
sed between ProE and Protel.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Fax (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
-Original Message-
From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]]
Sent
Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 25 July 2002 10:19 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Kudos
On 09:03 AM 25/07/2002 +1000, Igor Gmitrovic said:
>It goes both ways. PTC (PRO/Engineer) are about to release a PCB design
>package.
>
>Igor
It goes both ways. PTC (PRO/Engineer) are about to release a PCB design package.
Igor
-Original Message-
From: Brian Sherer [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 25 July 2002 1:40 AM
To: Protel EDA Forum
Subject: [PEDA] Kudos
I guess I'm in the minority, but I find the Protel user
a good one...
-Original Message-
From: Schmitt Michael [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 24 July 2002 5:45 PM
To: Protel EDA Forum (E-Mail)
Subject: [PEDA] To Forum Admin : Things getting too much OFF Topic here
Hey Folks ...
One uppon a time there was a Protel Eda Users Foru
Brian,
my bit to you is:
1. Use dual digital interface video card with LCD monitors. You will be able to work
longer ours. Apparently you will need that. You don't need many colours, so colour
processing speed is not an issue. You want stable image and no flicker.
2. M/B with 266MHz or higher
Ivan,
Writing dates as MM/DD/YY is the same as writing time as HH:SS:MM. It does not seem
logical. There should be linear ascendence or descendence in the order of things, IMO.
In Australia we have 240V/50Hz. Compared to your 120V/60Hz. We could discuss
frequency, but one thing is sure, the cu
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