Thanks, I thought I was loosing it...
heheh.. anyway, we are using it too, but I am fixing some old schematics and
didn't notice the dropping of the parts until checking the BOM. We put 'DNP'
into the part field when we wish not to stuff a part... it stands for "Do
Not Populate"... :)
- Bill Broo
> On 11:03 AM 2/12/2001 -0800, Hamid A. Wasti wrote:
>
> > It is a bad idea to use an inside radius same as your
> > router bit radius. This requires the router to come
> > to a complete stop and then start moving at 90
> > degrees. There will invariably be some chatter and
> > the router will cut
> Configuration file. There is a dialog box which can be used to select
> which Mechanical layers will be included in Printout definitions. But the
> layers so selected apply only *after* these have been set up, and as such,
> are not applied "retrospectively" to any currently/previously defined
Micky et al,
An important point here, that I just now realized: keepouts have NO EFFECT on planes!
Whether it's a keepout at the board edge, or
around a mounting hole, the gerbers do NOT get negative-copper in those areas. Which
is why everyone has to run these tracks around
the edges.
I onl
At 01:57 PM 2/12/01 -0800, Andrew W. Riley III wrote:
>Mr. Lomax,
>
>Yes, it is reproducible. The reset option has no effect.
>I have tried every option available to me even though it is only one sheet.
Still unstated is the complete set of Annotate settings. However, at this
point I'd be happ
this is a rookie mistake, BUT the board shop should have advised you
and/or just cut the plane back from the edges
this S.O.P.
don't forget that the plane is a negative, wherever there is nothing
there is copper, you draw non-copper
so the clearance rule doesn't really apply unless you would hav
Warning
Could not process message with given Content-Type:
multipart/mixed; boundary="=_16688250==_"
Alright, forget my message unless it is just to confirm that the automatic
process for adding Mech layers to printouts is broken. I found the
work-around by adding the layers within the individual drawing prints within
the Browse PCB Print.
Hi all,
now I believe a fair while ago I had se
Micky Blain wrote:
> 1. just go bit on a big order with power plane clearance. It seems that the
> gerbers generates the plane all the way to the edge of the keep out layers.
> Is there anyway to control the power plane and manually draw them in without
> doing them by split planes?
Yes, you p
Bryan Bernesi wrote:
> Hello,
>
> As another beginner to Protel, I am having problems trying to transfer my
> netlist from SCH to PCB. I am making a multi-layer board (2 signal, 2 power)
> with 24 exact modules. Each module has an isolated power and ground as well
> as two signal nets. (which
At 03:32 PM 2/12/01 -0600, Micky Blain wrote:
>1. just go bit on a big order with power plane clearance. It seems that the
>gerbers generates the plane all the way to the edge of the keep out layers.
>Is there anyway to control the power plane and manually draw them in without
>doing them by split
At 10:29 AM 2/12/01 -0500, Bryan Bernesi wrote:
>On another note, sometimes when I run the ERC some of my symbols are changed
>in my schematic, i.e.
>I have a PNP transistor (2N2904 symbol labeled as a TIP125) that changes to
>a different transistor symbol (taken from ), or a LED (a created s
> An important point here, that I just now realized: keepouts have NO EFFECT
on planes! Whether it's a keepout at the board edge, or
> around a mounting hole, the gerbers do NOT get negative-copper in those
areas. Which is why everyone has to run these tracks around
> the edges.
>
> I only recen
Brad Marshall wrote:
> Hello,
> I have a person here that wants a 50mil X 250mil rectangle plated
> through hole. I am having trouble figuring out the best way to do this
> with Protel so that the board house will know what I want. Any
> suggestion/comments are appreciated.
You'd better cont
Sorry folks,
I just sent a file to the group instead of my work address. Too late in the
evening...Many apologies. It's benign, but hopefully the forum admin can kill the
message before it's resent...
Irreverence for the pustule-filled decrepitude of the patriarchy is a proud, 400 yr
trad
Andrew,
I hope it really WAS just a screwup and nothing malicious. Just for grins, I
went ahead and opened the schematic file on an isolated machine and found that
it delivered a nifty little trojan...
I just got done cleaning my system and documenting what I found along the way.
It did appea
> From: Andrew J Jenkins <[EMAIL PROTECTED]>
> To: Multiple recipients of list proteledausers
<[EMAIL PROTECTED]>
> Sent: Tuesday, February 13, 2001 3:37 PM
> Subject: [PROTEL EDA USERS]: Hirose almost there
>
> Irreverence for the pustule-filled decrepitude of the patriarchy is a
> proud, 400 yr
Iris,
the TLC271 has programmable bias setting capability. If you do not need this
feature for simulation take the LMC6081 from National, which is close to the
Texas OP. The model is supplied by protel with the standard simulation
models for "OPAMPS", to be found in the ..\Design Explorer 99
SE\L
Hello Brendon,
Thank you for your response to my question.
It is logical that all modules have a unique RefDes. When I spoke to Christi
Cassares at the Protel Customer support she showed me how to easily update
the RefDes from U1 to U1_1.
(all RefDes are set as ?)
copy the module as many times
> So, to keep copper from the board edge on the inner planes, which is not a
> bad idea :-), one places track around the board edge. Conveniently, as
> noted by another, this can be nothing more than a blown up version of the
> keepout or board outline. I've always placed this on the plane layers
Hi guys -
Hi a.j. -
yes It's me, again - "Robi is doing the upgrade dance" - that's what you
called it, didn't you, a.j.?
Anyway -
you guys only ever talk about the good things of W2k as an operating system.
Could someone please give me the down-sides of it, as well.
, couple of questions -
Will
I got an error that said "access violation at address OE271BF0 in module
AdvSch.dll read of address 0046" and now Protel won't open any file or
respond in any other way. Any suggestions. Should I reload Protel? I was
just starting to get some progress and had my first board ready for layout
At 05:40 PM 2/13/01 +1100, Geoff Harland wrote:
>The idea of putting tracks on a Mechanical layer, and then including the
>contents of that (Mechanical) layer with just *some* of the Gerber files
>produced, to wit, the (Gerber) files produced from the internal power plane
>layers (only), raises t
Micky Blain wrote:
>
> I have deleted a power plane from my design. It seems that SP6 is not taking
> this off of the design. I think I remember this subject being discussed but
> I was swamped at the time and it was a few weeks back.
>
> Does anyone know how to get the plane off the design?
Op
I have been trying to send this for over four hours. Please accept my apologies if it
gets duplicated as our ISP seems to think [EMAIL PROTECTED] does not
exist.
Robi,
> Will W2k tolerate modem-sharing?
Yes. ICS is included with W2K, though I recommend and use a hardware solution
instead.
Thanks for the kind words.
I was not too concerned about looking foolish, I KNEW I had a virus and it
appeared at the same time I opened the schematic file in question. I did not
understand how it happened, but wanted to warn the rest of the list members
*just in case* there was some new deliv
On 09:50 PM 2/13/01 +1000, Robi Bittler said:
>Hi guys -
>Hi a.j. -
>yes It's me, again - "Robi is doing the upgrade dance" - that's what you called it,
>didn't you, a.j.?
Yes. No offense intended, of course. As always, just trying to keep some humor alive.
>Anyway -
>you guys only ever talk ab
I like the idea about the vacation, could I forward that ot my boss? With
80+ hours a week the norm here I could use a week off!
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Abd ul-Rahman Lomax
Sent: Tuesday, February 13, 2001 3:16 PM
To: Multiple recipient
Ok... I haven't followed this... but I don't want to go back looking either
;)
It sounds like you ran a netlist into a routed board.
The netlist only has net info for the components and their pads.
So... the tracks are left with the net NoNet... this will cause a short
circuit violation and a c
you have to put it to NO NET before you can remove it from the layer
stackup dialog
I think you have to remove all entities from the plane too
Dennis Saputelli
Micky Blain wrote:
>
> I have deleted a power plane from my design. It seems that SP6 is not taking
> this off of the design. I think I
At 01:01 PM 2/14/01 -0800, Brad Velander wrote:
>Dennis,
> can you be more specific in your "learning" the board? I think I
>know what you mean but I am not exactly sure there is not some other process
>that I don't know about. Do you mean generating a netlist from the existing
>board conn
sorry, it's my lame term for the 'update free primitives from component
pads' function in the netlist manager menu option
Dennis Saputelli
Brad Velander wrote:
>
> Dennis,
> can you be more specific in your "learning" the board? I think I
> know what you mean but I am not exactly sure t
PVDTS -- (Post Valentines Day Traumatic Syndrome).
regards,
Tim Hutcheson
Institute for Human and Machine Cognition
40 S. Alcaniz ST.
Pensacola, FL 32503
[EMAIL PROTECTED]
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* This message sent by: PROTEL EDA USERS MAILING LIST
*
I've quoted the full headers and cc'd this to Mr. Lundsten as well; perhaps
this will be of some use.
Sometimes list servers can be configured to send copies of incoming posts
to all subscribers except the author. Usually, I think, the default is that
the author also gets a copy; on yahoo/egro
Apparently it's possible to put a sheet entry called e.g. RST# and
regardless of whether the corresponding sheet has a RST# port, the nets
will be connected. This relates to my earlier post regarding an ERC
check for unmatched ports and sheet entries.
Is this sensible? I can't think of any good a
Andrew J Jenkins wrote:
> I'd still like to know some more specifics regarding optimizing this new
> rule. My 31's DO live a much shorter life than the 62's, on average, and I'm
> sure everyone else would ultimately benefit from the information too. A rule
> is only useful if its substance can be
> -Original Message-
> From: TSListServer [mailto:[EMAIL PROTECTED]]On
> Behalf Of Peter Bennett
> Sent: Tuesday, February 13, 2001 8:14 AM
> To: Multiple recipients of list ProtelEDAusers
> Subject: Re: [PROTEL EDA USERS]: having W2k installed, can I run...
>
>
> And I just discovered
I hope it doesn't give CR for a diode !
or IC for a U
so what do you do with a 3 pin regulator that looks like a Q?
I have taken to naming them Q or sometimes REG
if you name them U the assembly people look all around for an IC type
package
personally I like Z for a zener and TZ for a tranzorb,
> Yes, I think it is the same as I had with the company - logo on the
> schematic.
> In the sheet ( or library part ) there is a link to the graphic file and
not
> the
> graphic itself. Your collegue has probably not the same graphic in the
same
> path.
>
> Georg
I have also had similar experienc
if space allows why not just overshoot a bit in the corners, then a
rectangular part can fit snugly, I've done this.
Dennis Saputelli
Andrew J Jenkins wrote:
>
> On 09:52 AM 2/15/01 -0800, Hamid A. Wasti said:
> >Andrew J Jenkins wrote:
> >
> > > I'd still like to know some more specifics regard
Perhaps I should read ahead, instead of popping in so quickly. I see that
Mr. Wasti has at least partially answered my questions (under the subject
of Optimum Routing inside radius, was: Rectangle holes):
At 09:52 AM 2/15/01 -0800, Hamid A. Wasti wrote:
>...
>It is a fact of life that the smal
At 08:42 PM 2/12/01 -0800, Marty Beck wrote:
>I got an error that said "access violation at address OE271BF0 in module
>AdvSch.dll read of address 0046" and now Protel won't open any file or
>respond in any other way. Any suggestions. Should I reload Protel? I was
>just starting to get some
OK that is what happened, I will try and rename the plane prior to deleting.
Thanks!
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Le, Phan
Sent: Tuesday, February 13, 2001 4:10 PM
To: Multiple recipients of list proteledausers
Subject: RE: [PROTEL EDA USERS
Marty,
What did you do before the message?
I got that same message when I tried to open two design databases in
the same Protel window (99SE SP5). I think the second DDB was corrupted, but
regardless, I had to go use a back-up copy that I had. Periodically, I will
copy of
"Lloyd N. Johnson" wrote:
> I don't want to sound too critical here, but this sounds like mythology to
> me. Are you saying a router cannot stop and change directions without
> creating some kind of problem? I have been working with board vendors for
> 20 years and no vendor ever told me anything
Andrew W. Riley III
Talon Instruments
150 East Arrow Highway
San Dimas, California 91773
(909) 599-0690 [voice]
(909) 599-6529 [fax]
www.taloninst.com
[EMAIL PROTECTED]
ICQ#: 100686794
-Original Message-
From: Andrew W. Riley III [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, February 13,
??
Just checking, I've seen only a few posts from the forum today and that was
this morning.
Time is 5:09PM GMT
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* This message sent by: PROTEL EDA USERS MAILING LIST
*
* Use the "reply" command in your email program to
* respon
Just very busy here.
Brad Marshall
"Coleman, Tim" wrote:
> ??
>
> Just checking, I've seen only a few posts from the forum today and that was
> this morning.
>
> Time is 5:09PM GMT
>
> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> * This message sent by: PROTEL EDA USERS MAILI
I hope Ian Wilson fixes the link so it points to
http://www.angelfire.com/electronic/protelarchive/threads.html
...
Steve Smith <[EMAIL PROTECTED]> on 2001-02-14 02:44:15 PM
Please respond to [EMAIL PROTECTED]
To: Multiple recipients of list proteledausers
<[EMAIL PROTECTED]>
Hello David,
I would send you a file with my problem, but if you check some
of the emails that come in after, Mr.Lomax explains why the ERC would have
changed the component.
After I fixed that, the ERC hasn't changed the symbols in my schematic.
Very Kind Regards,
Bryan Bernesi
-
My apologies to the members of the list, and especially to Andrew Jenkins.
It appears that the trojan I picked up must have come from elsewhere. I have
tried reopening the schematic file in question and cannot repeat being
infected.
It must have been a coincidence that the trojan showed itsel
Thanks for qualifying my experience level for me, where are you located so I
can turn my carpet your direction!
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Dennis Saputelli
Sent: Monday, February 12, 2001 9:20 PM
To: Multiple recipients of list proteledaus
"Lloyd N. Johnson" wrote:
> Message text written by Hamid
> >It is a bad idea to use an inside radius same as your router bit radius.
> This
> requires the router to come to a complete stop and then start moving at 90
> degrees. There will invariably be some chatter and the router will cut
> i
Thanks for the explanation Geoff. I had expected the same operation as P98
where checking the selection added the layers to the print subsequent to
checking the box. Just to make sure I understand your explanation, the check
selection for adding Mechanical layers to final prints will only add the
On 07:07 PM 2/13/2001 -0800, Andrew Lowy Sybrandy wrote:
>All,
>
>I just went to the ANSI site, and had no luck finding my way around. Does
>anyone have some quick advise on how to navigate through this site
>www.ansi.org to actually find the ANSI Y32.16-1975 standard? I typed Y32.16
>on their s
At 12:28 AM 2/13/01 -0500, Andrew J Jenkins wrote:
>Sorry folks,
>
>I just sent a file to the group instead of my work address. Too late in
>the evening...Many apologies. It's benign, but hopefully the forum admin
>can kill the message before it's resent...
Forum administration almost does not
hey, "rookie" isn't a pejorative, in sports they are the team's future
I did not intend to insult or demean you, sorry if it came off that way
besides, my main point as stated was that the board shop did not handle
this situation well
they should have advised you and/or fixed it properly, not inc
Hi Lloyd,
While I can't speak from direct experience that this is true in the board
manufacturing industry, it certainly is true in the metal machining
industry. We manufacture photoplotters to very tight tolerances using
highly accurate CNC machine tools. Any time a radius is required, we insu
Geoff Harland wrote:
>
> That is not the only grumble that I have about the CAM Manager server, and
> it is not necessarily the biggest shortcoming associated with it. But what I
> have written in this post is something to be kept in mind in the event that
> the contents of one or more Mechanical
Robi Bittler wrote:
>
> Hi guys -
> Hi a.j. -
> yes It's me, again - "Robi is doing the upgrade dance" - that's what you
> called it, didn't you, a.j.?
> Anyway -
> you guys only ever talk about the good things of W2k as an operating system.
> Could someone please give me the down-sides of it, as
Sorry for the reply, I need to show more self control in this matter.
You are 100% correct it is a rookie mistake!
I have already read one person that checked their design. Because of the
willingness of an old dog to admit this ROOKIE mistake! So if that person
saved some money and time I can ea
I was reminded again today of the old Tango complete route command. It was
assigned to the forward slash key and it would interrupt the current route
and reduce the display rat's nest connection line to track. It really
shined when it came to doing gridded design with round off-grid pads. You
Lloyd,
You might want to find the ANSI standard (do a Yahoo web search, etc.) for
reference designators. It should help.
John
-
John R. Lemburg,Sr. Hardware Engineer
Avistar Systems, Inc., Madison Building
15851 Dallas Parkway, Suite #600
At 11:14 PM 2/12/01 -0600, Jon Elson wrote:
>In a hierarchical schematic, you need to connect the power to the child sheets
>on the master sheet(s), just like you connect the signals.
This is true if normal net labels are used to establish power. However,
power ports and hidden pins establish g
You're trying to load a PCB file, as the menu indicates. That is not the
correct thing to do.
You want to first add the external netlist from Orcad (using the tango
format) to the Protel DDB. Click on the DDB name or documents folder in
Protel 's explorer. Use the file import and bring in the net
No problem with the "rookie" I was just a little less talerent becasue it
cost the company 25,000 and the guy that made the deceition didn't take the
blame. It hit me full force. I to was wondering why they didn't contact me.
They had made contact with a guy in another state! Oh well this was one
I have found that I can avoid the relocated overbars by ensuring
that PDFwriter is configured to embed all fonts, with no exclusions.
It makes the PDF a bit bigger, but at least I have a distributable
schematic!
On the subject of naming conventions, we have numerous CAD packages
here (IC design
Lloyd,
We try to use ANSI Y32.16 (www.ansi.org) whenever possible.
Steve Smith
Product Engineer
Staco Energy Products Co.
Web Site: www.stacoenergy.com
> -Original Message-
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, February 13, 2001 12:25 PM
> To: Multipl
My Co. decided to spring for some simulation software (thermo and signal
integrity), and I wanted to get the group's thought's.
1. What is the best
2. What works with Protel (this is not requirement but would be nice)
3. How much
4. Price/Performance
5. The ability for the software to give advice
At 12:24 PM 2/13/01 -0500, [EMAIL PROTECTED] wrote:
>Hi all,
>Even the term "Designator conventions" smacks of oxymoron. I am trying to
>create a company library database and SOP for design. I have many Engineers
>with various cultural backgrounds, some of which use some pretty weird ID's
>and sym
On 09:52 AM 2/15/01 -0800, Hamid A. Wasti said:
>Andrew J Jenkins wrote:
>
> > I'd still like to know some more specifics regarding optimizing this new
> > rule. My 31's DO live a much shorter life than the 62's, on average,
> and I'm
> > sure everyone else would ultimately benefit from the infor
Being unwise in the ways of OrCad, my assumptions
may be wrong, but File/Import/*.PCB will import a PCB?
If you want to get a "netlist", you should use
Design/Load Nets...
Does OrCad assign a ".PCB" extention to it's netlist. If
you are new to Protel, you should know Protel uses the
extention ".
I have deleted a power plane from my design. It seems that SP6 is not taking
this off of the design. I think I remember this subject being discussed but
I was swamped at the time and it was a few weeks back.
Does anyone know how to get the plane off the design?
Micky Blain
PowerSmart Inc.
*
At 01:32 PM 2/13/01 -0600, Micky Blain wrote:
>I have deleted a power plane from my design. It seems that SP6 is not taking
>this off of the design. I think I remember this subject being discussed but
>I was swamped at the time and it was a few weeks back.
>
>Does anyone know how to get the plane
My personal take on hidden pins is that they should never be used.
All our symbols have a separate power part (unless it's logical
for the power pins to be on the main symbol part), which needs to
be explicitly placed on the schematic sheet. We do this to avoid
automagical connection of power pins
Yes, I think it is the same as I had with the company - logo on the
schematic.
In the sheet ( or library part ) there is a link to the graphic file and not
the
graphic itself. Your collegue has probably not the same graphic in the same
path.
Georg
[EMAIL PROTECTED]
> -Urspr ngliche Nachricht
before you can delete a power plane, you have to re-assign the plane to no
net.
If you don't do this first & delete the plane, Protel will remove the plane
of the list temporary. When you get back to Layer Stack Manager, the power
plane will still be there (I hated that).
Phan Le
-Original M
On Tue, 13 Feb 2001 15:05:10 -0800, Andrew W. Riley III wrote:
snip...
>> Will W2k tolerate dual screen-setup with totally independed
>> screen-settings?
>
>Yes. At home I use NVidia's GeForce2 MX (a dual-port w/TV-out) running a 20"
>Silicon Graphics @ 1152x864 and a 15" Magitronics @ 800x
Sometimes a consistent crash on startup of Client is due to a defective
database which is being loaded automatically. There may be a key command,
as I recall, which will interrupt the startup, but I don't recall what it
is. It isn't ESC.
[It ought to be.]
In any case, I took my file Windows/C
Iris,
yes, i have seen this too.
It seems to be a bug, because the simulation results look ok.
Lets report it to Protel.
GMIN is one of the spice variables. Actually its the conductance (1/R) of
the resistors that spice places in parallel with any semiconductor p-n
junction during the simulation
we use a 50 mil track centered on the board outline, you can just clone
the board outline to the plane layers and use a global to thicken them
I think I recall hearing that 25 mils is a desirable amount for
clearance to board edge.
here's a question, what do you do with planes in the finger/ padd
At 10:46 AM 2/13/01 -0800, Dennis Saputelli wrote:
>on the other side I once had a shop put a board on hold for a week
>because the fab print said 8.000" but they said the board Gerbers
>measured 7.999"
>I pointed out that they have a 5 mil outside routing tolerance, but they
>responded that they
At 02:38 PM 2/13/01 -0500, Bryan Bernesi wrote:
>Now, I fixed all my ports, net labels, RefDes, etc...
>When I try to Update PCB I get the errors "Net Already exists"
>What do I do?
>
>Just to let you know my scenario, my PCB already has all the components
>placed as I want them...
>The onl
Most important is an 'annotate components' before 'update pcb'
Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
David Cary wrote:
>
>
> Dear Greg Olson,
>
> I have been using Protel 99 for a little over a year now, and I've always used
> the "Design | Update PCB" and "Design | Upda
Bryan Bernesi wrote:
> I have 24 isolated -6V nets that I would like to pass on the power plane,
> and 24 isolated GND that i would like to pass on the GND plane. my question
> is, can I use the power plane as a regular internal plane? i.e. passing
> traces on the plane layers?
I see two ways to
At 01:47 PM 2/13/01 -0800, Forum Administrator wrote:
>There are many alternatives to attaching a file to a discussion group
>post, but if you feel you really must, at least be considerate of your
>fellow subscribers and keep attachments under 50K and ALWAYS compress
>(zip) the file.
Let me p
> At 01:47 PM 2/13/01 -0800, Forum Administrator wrote:
>
> >There are many alternatives to attaching a file to a discussion group
> >post, but if you feel you really must, at least be considerate of your
> >fellow subscribers and keep attachments under 50K and ALWAYS
> >compress (zip) the file.
>
I need to draw schematics in 4 different languages. The Bom must be
absolutely different from language to language. I can accept that the field
"Description" is the same for all of them.
I thoutgth the differente choices:
Using the "Read Only fields" but I already used almost all of them.
Generat
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