Mike, I use Acrobat 4.0 (Distiller) on win2000 to print schematics, no problem.
> -Original Message-
> From: mike ingle [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, July 10, 2002 9:49 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] PPC to word insertion
>
>
> I reccomend adobe acrobat
FWIW, we've generally found Acrobat Distiller to be more reliable/accurate
than PDF Writer when handling graphics, both from Protel & other apps.
> -Original Message-
> From: mariusrf [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, July 11, 2002 1:16 PM
>
> I've seen this too , although in a
Most of the ICs we use are only rated to 85 deg. C operating range. I'd
hate to troubleshoot a board running 130degC components.
> -Original Message-
> From: Danny Bishop
> Sent: Wednesday, July 17, 2002 6:21 PM
> hi
>
> Basically FR4 should run up to 130degC, and your semiconductor can
There's a bunch of DXP tutorials, etc., at
http://www.protel.com/resources/tutorials/index.html, with no ATS required;
maybe there's others you were referring to?
> -Original Message-
> From: Don Ingram [mailto:[EMAIL PROTECTED]]
> Sent: Saturday, August 03, 2002 3:52 AM
> To: Protel EDA
If changing drivers fixes it, then it's NOT Protel's problem. Similarly, if
changing printer settings fixes it, it's NOT Protel's problem.
The problem may only appear in Protel because it might use unusual
parameters or unusual series of calls to the printer driver. The
application code in a Wi
re lease/support -- the difference is that if you stop paying the lease, you
cannot legally continue using the software. In fact, depending on the
contract, if the company goes out of business (or drops the product) you
might not be able to legally continue using it. To take an extreme example,
just a thought, you should have SP6 installed.
> -Original Message-
> From: Robert Ritchey [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, September 10, 2002 4:50 PM
>
> Hi all,
> I've had 99SE for almost a year but have used it very little. I
> am trying to use it now to make a composite of
I haven't done a lot of boards, but why would you have overlapping polygons?
There are cases where Protel will (must?) repour all the polygons -- what
order should it use then? (And will some other designer looking at this be
able to figure it out?)
-Original Message-
From: Scott Ellis [m
One other thing about Sierra Proto Express (link below), they have some
fairly sophisticated software checking the Gerber. On one design we sent
them they caught that 2 track segments, while touching, only BARELY
overlapped -- the narrowest point of overlap (of the rounded track ends) was
much le
You can use "Tools | Convert | Explode Polygon to free Primitives" to
accomplish that.
-Original Message-
From: Scott Ellis [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 5:33 PM
My next approach is to edit the text version of the PCB file, grab all the
track primitives t
Just a tip to all computer (not just Protel) users:
Anytime I've lost data (from any program, any reason) and have to use a
backup file, the FIRST thing I do (BEFORE opening the backup file) is make a
COPY of the backup, to some other directory, preferable a different drive,
and mark it read-only.
Jon's point was that you'll need to do this in 2 passes. First, set grid &
rules that will optimize your via placement, and run the autorouter with
ONLY "Fan out used SMD pins" checked -- clear all the other pass
check-boxes. See how the vias look, maybe adjust rules/grid. You might try
a speci
I don't use SourceSafe for protel, but for other stuff -- just a note that
there's an option to turn off the 'read-only' setting for un-checked-out
files. But having it read-only doesn't seem like a bad thing in that case.
-Original Message-
From: Brooks,Bill [mailto:BBrooks@;dtwc.com]
Se
Any chance that on (Arrow) | Preferences, somehow "Save Preferences" was not
checked?
-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Thursday, November 21, 2002 7:35 PM
To: Protel EDA Forum
Subject: Re: [PEDA] What else is under the hood
ok , here goes .. my (I
Here's an old post about that...
-Original Message-
From: Isabelle BAUDRY [mailto:[EMAIL PROTECTED]
Sent: Wednesday, December 05, 2001 12:48 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Sort hierarchy
Here is the way I reorder sheets in a project :
Open the top sheet (project.pjt)
Use the
a permanent one).
Good idea about creating the union -- something I usually forget to do.
Dwight Harm
Trax Softworks, Inc.
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 04, 2001 3:57 PM
We take the view that any socketed items are actually part
Richard,
This might get you what you want... go to Design | Rules | Other, add
"unconnected pin constraint" with a scope of Whole Board. Then on Tools |
DRC, check "unconnected pins", & you'll get a list of violations for pins
that have no connecting tracks.
Dw
quot; There's no mention of it mattering whether
or not the pin is listed in a net. Also, the help file does not document
this rule at all. (It does list the other 2 rules on the "Other" tab.)
(P99SEsp6)
I hope Protel support will comment on what they believe this rule is
SUPPOSED
For an additional visual reminder when building such a multi-pin part, I use
one "dot" (circle) style pin & the rest regular, so the schematic symbol has
a pin going through the circle.
Dwight.
-Original Message-
From: Geoff Harland [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 18,
I was wondering, Mark, was the issue that you wanted to test the nets before
assembly? Or was it just in case of problems after assembly? For the
second case, you might use a virtual short on the top or bottom layers,
which could be cut if need be.
-Original Message-
From: Mark E Wither
build
my void out of multiple rectangular fills.
Am I missing something?
(I've also found I have to turn off the display of the layer with the large
polygon if I want scrolling to be reasonably responsive.)
TIA,
Dwight Harm
Trax Softworks, Inc.
* * * * * * * * * * * * * * * * * * * * * *
Only schematic pages that are open when you hit "Update Schematics" will be
changed. I think it's always been like that. I also found that "Update
parts in Cache" only affected the open schematic pages, at least after I was
in this 'partially updated' state.
-Original Message-
From: Jon
I have a board that was mostly auto-routed. I'm finishing it up, and find
that if I have "automatically remove loops" checked, when I finish manually
routing a net (right-clicking once), any vias I put down in the process are
deleted! If I turn OFF loop removal, the vias remain. The problem occ
ically to the program defaults.
BTW, a member of the Protel support staff took the initiative and contacted
me after seeing my post to the list, and worked to recreate & document the
problem. I'm impressed!
-Original Message-
From: Dwight Harm
Sent: Mond
Schematic, PCB, Powerprint, CAM Mgr, Autorouter, Camtastic (a bit).
PLD I used a bit, but it was easier to switch to Xilinx's tools than to
figure out how to get intermediate files from one to the other. (But it's a
pain using Xilinx's schematic capture.)
-Original Message-
From: Edi Im
Not doing anything too large, but mostly use autorouter, with some manual
pre-routing. 300+ components, SMT & thru-hole, 4-layer, mixed
analog+digital. On the dense side (for me), 1200 pads on 5x7 board -- I'm
happy to let the autorouter find a way! (Usually gets it about 98%.)
-Original Mess
nk to our web development team to fix. For future
reference for creating a hierarchical schematic please refer to page 131 in
the Protel 99 SE manual.
- Original Message -
From: "Dwight Harm" <[EMAIL PROTECTED]>
To: "protel support" <[EMAIL PROTECTED]>
Sent:
I find the Print mgr very useful & reliable; you can carry PPC (Print mgr)
files forward from one design to the next & reuse them, so I'm not sure what
you mean about having to repeat the setup. My one complaint is that it
insists on rebuilding all the previews whenever the slightest change is
ma
One problem with a "power table" is that it's only "comments" -- it's not
used to generate the netlist. It's quite possible a designer could change
the power connection for the symbol but forget to update the table, or
vice-versa. Or even change the symbol in the library, and the table, but
some
Steve, here's a comment from my archive that might help:
-Original Message-
From: Frances Wheeler
Sent: Thursday, February 01, 2001 5:10 PM
To: Multiple recipients of list proteledausers
Subject: Re: [PROTEL EDA USERS]: Imperial <-> Metric & Wheel Mouse
That is easy -- assign the wheel b
Some ideas that might help...
- Any chance you have 2 components with J3 designator? Also double check
the library symbol regarding both pin names AND numbers -- maybe there's a
duplicate "10".
- Have you run ERC? Make sure the error matrix is set to catch as many
errors as po
This list tends to be a little quiet on weekends, so I'll have a go at
answering...
I think most of the experienced users find it faster to create their own
footprint from the manufacturer's datasheet than to try and find it in the
Protel libraries. It's certain that if you do much design, you'l
Some suggestions that may or may not be appropriate/helpful --
-- if the keepout is just to control polygons, maybe it'd help other
problems to make it VERY thin, say .001 mil?
-- somewhat similarly, if holes just need to "touch" the keepout (not
actually overlap), then you might be able to move t
Is it possible the two track segments didn't start/end at exactly the same
coordinates? I've seen odd handling of tracks in other situations when the
two ends overlapped but were not *exactly* co-located.
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Thursday, D
>From Protel website:
"
- 20% discount on your Protel full-suite new license or upgrade*
- 12-months free ATS membership (retail value US $1,995) which guarantees
you the next Protel version FREE!**
"
-Original Message-
From: Ted Tontis [mailto:[EMAIL PROTECTED]]
Sent: Thursday, Decembe
I've had over a dozen emails from Altium support in the last couple months,
regarding 3 or 4 different issues/questions. The problems weren't all
resolved completely, but the personnel are definitely making an effort to
respond constructively.
I have to say there was a "dry spell" about a year a
Setting this color (Options | Colors | Connections) has no effect on my
system (99SEsp6). I seem to recall a discussion about this some time ago,
and no one got it to work.
So, Tom -- does this actually work for you?
Dwight.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROT
Just to be clear, you mean the ratsnest lines show as dotted or dashed --
not hidden -- right? I've never seen that happen, even for partially-routed
nets. Does it matter what layers are being displayed? What if you turn off
the grids? You might check the "layer drawing order" -- mine has
Conn
Dave,
What you're doing sounds interesting and possibly useful (to myself/others),
but it also sounds a bit dangerous. Could you explain a bit? Do you have
the same footprint name in 2 different libs representing different physical
layouts?
I say dangerous because I've had P99SE change the libs
I'd tend to agree with Ian. If it's a one-shot thing maybe not ... but if
it's going to stay around, maintenance will be a lot more understandable if
it's split. Sometimes an easy way to split something like this is to copy
the whole project, then delete the unneeded parts from each copy to get
Bob,
Two points about this --
1) The list of footprints in the library symbol is merely possible
choices -- you don't have to use any one of these. So changing the
footprint list in the library should NOT update all the footprints for those
symbols in the schematic.
2) Use global edit if you real
I don't usually use this rule -- I rely on the schematic ERC to catch
unconnected pins. However, trying it out, I think I see what you mean.
The rule applies to whatever you select -- whole board, or some pad class,
etc. What would be more useful, it seems, would be to have it check all
pads exc
Unfortunately, driver problems often only show up in one or two programs,
especially those programs that stress the driver. Schematic & PCB output
(print & display) is certainly graphically intensive compared to your
average Windows program. Similarly, if you talk to a PC-gamer, they can
tell yo
I use the autorouter often, but:
- I only use "Route All"
- Boards are not too complex, e.g., 5"x7", 4-layer, some fine-pitch but no
BGA.
- I use a layer-specific keepout, but I pre-routed all the nets within that
area.
FWIW, I did a Report of my design rules, and the ones marked "Rule Followed
B
If you're using a ddb, once it's imported you can rename it from within
Design Explorer -- just right-click in the design tree & choose Rename. If
the sch hierarchy doesn't seem to be intact, then after renaming the sch
entries, right-click on the ddb entry & choose Refresh. If that doesn't do
i
It is from CO, and most of the tip/ring tracks are separated more than that,
but the SMT jack we use (from AMP) has only a 15mil gap between the pads, so
the rule for that part of the net has to accomodate that spacing.
-Original Message-
From: Bob Wolfe [mailto:[EMAIL PROTECTED]]
Sent: S
It might be a file association problem. I think if .sch gets associated
with a non-Protel program, it can have effects such as you described. Does
a .sch file in Explorer show a schematic icon, or something else? Some
scheduling programs use .sch, so installing or updating such a product could
If copy & paste doesn't work, save the spreadsheet, then export it to
external file & load it into excel.
-Original Message-
From: Georg Beckmann
Sent: Monday, January 28, 2002 10:41 PM
Hi,
Abdulrahman Lomax told me how to export data to spread.
When I export the data from a schematic
It's not a bug in Windows or Protel -- it's simply a design decision someone
at Protel made. There are times when it's useful to run multiple copies of
Protel, so it's good that they allow that. Since you can use drag-n-drop
from Explorer to open a file in an existing instance, it's not unreason
It seems like sch parts already have a persistent handle -- this is used by
the synchronizer to match to the PCB, right?
Further comments embedded...
> -Original Message-
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, January 30, 2002 10:22 PM
> Sure, GUIDs wo
The fix apparently was that you can do a Save -- you don't have to do a Save
As or Save Copy As. BUT you still MUST do the Save before exporting. You'd
think they would have fixed that at the same time.
> -Original Message-
> From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
> Sent: Sunda
If anyone else has to maintain this, I think it'd be very confusing to have
2 footprints that together match 1 part. If you do take this approach, at
least "group" the footprints so they can't readily be moved separately.
As far as making the schematic ugly with an integrated part, you could mak
I use the synchronizer (from sch to PCB) all the time with "update component
footprints" checked, and it never puts back "the first footprint on the
list". It respects whatever footprint is specified in each schematic
symbol.
> -Original Message-
> From: Bob Wolfe
> Sent: Sunday, Februar
Looks like a bug to me, too. I understand what Matt is saying -- in
Wordpad, for example, when in overwrite mode, pressing Return does NOT
overwrite the next character, but instead inserts a carriage return. In
Protel Text Editor, however, neither one happens (in overwrite mode).
Pressing Return
I'll second Terry's suspicion -- I have one machine with full Acrobat
installed, and the Insert | Object list includes "Adobe Acrobat document";
but on a second machine with only Reader installed, it is NOT in the list.
> -Original Message-
> From: Terry Harris [mailto:[EMAIL PROTECTED]]
You might try disabling all your Design rules and see if it works. Does the
board have DRC errors? If you set routing mode to "Ignore obstacles", does
that make a difference?
> -Original Message-
> From: Michael.Payne
> Sent: Monday, February 11, 2002 1:00 AM
>
> Hi John, All,
> I've al
I see I opened my mouth just wide enough to get my foot stuck... Brad et al
are quite right, it is (or should be!) well defined and there's definitely a
bug there. I confirmed this on one installation (win98, 99SEsp6). One
additional note -- the bug occurs even when "remove dead copper" is not
c
The one problem I see is that KB item 1985 indicates it is a user error:
"Folders cannot contain invalid characters such as apostrophe's." Since
Windows allows it as a filename character, it's not invalid; other programs
handle it ok. Also, equal signs cause a similar problem. (win2000, 99SEsp6)
If you have a sch page that matches the section you repeated on the PCB, and
you followed some pattern in designators, then in sch you can copy the page,
then use Tools | Annotate, Advanced tab (I think) to renumber the sch parts
in a matching way. Once designators match, do Design | Update PCB t
er correctly, this does not work for me either (just tried it),
>
> -Original Message-
> From: Dwight Harm [mailto:[EMAIL PROTECTED]]
> Sent: Friday, 14 December 2001 6:23 PM
>
> Setting this color (Options | Colors | Connections) has no effect on my
> system (99SEsp6). I
> Sent: Friday, February 09, 2001 12:38 AM
> Subject: Re: [PROTEL EDA USERS]: Many docs open makes tabs unreliable. Sp6
bug?
>
> Confirmed. I experienced the same. This is a new bug introduced in SP6.
>
> Gisbert
>
> "Dwight Harm" on 09.02.2001 09:19:00
> Subject: [PR
re Findfast - MS Office (& other products, perhaps) will install this -- it
indexes all your files; check for a Control Panel applet "FindFast" to
configure it. (I uninstalled it.)
> -Original Message-
> From: [EMAIL PROTECTED]
> Sent: Monday, February 18, 2002 4:22 PM
>
> Ive seen that w
I'm relatively new at PCB layout, so I'd like to verify -- aren't
under-the-component vias fairly common nowadays, particularly with
fine-pitch ICs and BGAs? The autorouter puts 'em there all the time, so it
MUST be ok! ;)
> -Original Message-
> From: Thomas [mailto:[EMAIL PROTECTED]]
>
I just meant under the body of the component, not in the pad.
> -Original Message-
> From: Ted Tontis
> Sent: Thursday, February 21, 2002 7:34 AM
>
> There are quite a few problems with via in pad...
>
> -Original Message-
> From: Dwight Harm
>
Enhancement suggestion:
Seems like a lot of these polygon problems would be solved if we had an
option to display all polygon outlines/vertices. Just a checkbox on display
options.
> -Original Message-
> From: Brad Velander [mailto:[EMAIL PROTECTED]]
> Sent: Friday, February 22, 2002 6:5
Would it help to solve the laser print problem? If so, here are some ideas:
In page setup, have you tried 'fit to page', or setting explicit scaling?
Is reasonable paper size/orientation selected?
Re plotter, do other Windows apps print to it ok? E.g., try printing a bit
of text from notepad.
>
I'd suggest fixing all 12 & see if board info goes to zero, too. (Sounds
like the net is not set for your fills.)
> -Original Message-
> From: Juha Pajunen [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, February 28, 2002 11:57 PM
>
> Hi,
>
> Protel99SE + SP6 and W2K. DRC-report says that I
If selection only highlights the edge, that's probably because the Tools |
Preferences | Display, "Hightlight in full" option has been turned off.
As to tracks on turned-off layers showing when the net has the focus (not
selected), that happens on my system, and I think it always has -- BUT, it
d
I've used it occassionally. One thing it can do that global edit can't is
select by "less than" or "greater than" comparisons, e.g., for track width
or hole size. Also, the ability to save/name the selection criteria is
handy sometimes. Note, however, that the queries aren't stored with the PCB;
In Mr. Doyle's example, the "AND" is not acting as a "logical" AND -- it's
an OR, that is, the result is the addition (union) of the selections, not
the intersection.
HOWEVER, I then tried using the same "object type" in multiple selections,
and in that case, it WAS a boolean AND. For example:
This was discussed on the list around 1/25/02. There was a note from
someone indicating that Camtastic has a bug related to path length; here's
the text:
"To stop this from occurring, you need to keep the entire path name, from
the drive letter to the last character of the filename's extension
(
Yeah, that's a known bug, & I don't know of any workaround.
> -Original Message-
> From: rimas
> Sent: Thursday, March 14, 2002 6:50 PM
>
> quick question - i've noticed some very annoying behavior recently when
> i've got a bunch of files open and i'm trying to switch between them by
> c
This sounds great to me.
> -Original Message-
> From: Don Ingram
> Sent: Thursday, March 14, 2002 7:32 PM
>
> Item: Addition of menu/mouse button behaviour to Layer tabs on PCB module
>
> Technique:
> 1. Add layer Tabs to the PCB window according to the settings in the
current
> Layer Dia
Have you checked the library list in PCB? Double-check footprint spelling?
> -Original Message-
> From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
> Sent: Sunday, March 17, 2002 7:43 AM
> To: 'Protel EDA Forum'
> Subject: [PEDA] footprint trouble
>
>
>
> hello,
>
> i'm finishi
The .ldb is a "lock" file created by Access when Protel opens a ddb, and is
deleted when Protel closes the ddb.
If you want to back up all your "settings", besides all the *99se.* files in
your Winxx directory, there are one or more files in the
\designExplorer\system\ directory as well, such as
You can also make toolbar buttons to toggle one or more layers on & off,
which might be quicker for you.
> -Original Message-
> From: Stephen Casey [mailto:[EMAIL PROTECTED]]
> Sent: Monday, April 08, 2002 9:16 AM
>
> Thanks Bob,
>
> > You need to go to the layer dialog (shortcut 'L') the
Another idea similar to Ian's (5)-- if the footprint's pads don't work well
(e.g., it's a large footprint with pads around the edge), you could add tiny
(zero size?) free pad(s) in the interior, put them into a pad-class, then
use a via/pad-class clearance rule. Unfortunately, the pads will proba
Only open sheets in the schematic will be updated by "Update Schematics";
same with "Design | Update parts in cache". So be sure all sheets are open
first (easy way: File | Open Full Project).
> -Original Message-
> From: Robison Michael R CNIN
> Sent: Tuesday, May 14, 2002 12:04 PM
>
>
You might look around for other files with the same filename. Access/protel
will create a .ldb file when it opens a ddb, with the same filename as the
ddb. Maybe there's a "bad" .ldb file that's not getting cleaned up after
the compress.
> -Original Message-
> From: [EMAIL PROTECTED] [m
Check out the help topic "PCB Design Layers".
The "multilayer" is a Protel concept, a bit strange at first... it shows
things that exist on more than one layer -- this is mainly holes, pads, and
vias.
Layers you mentioned that aren't in the help...
I've never seen a layer called "Part Numbers";
Paste MASK and solder MASK layers are negative layers -- what you see are
the holes (voids) in the layers.
Solder mask is the (often green) stuff that covers most of the board
surface, EXCEPT for pads or anyplace else you want solder applied. So
Protel's solder mask layer shows what's NOT covere
If I understand this, it still can't work. The paste-mask stencil has an
opening for the pad, and you want a circular block in the center of the
pad -- but there's nothing to support it.
> -Original Message-
> From: David W. Gulley
> Sent: Saturday, June 01, 2002 11:13 AM
>
> Richard Sum
would you place a circle on the paste mask layer?
>
> Dwight Harm wrote:
>
> > If I understand this, it still can't work. The paste-mask stencil has
an
> > opening for the pad, and you want a circular block in the center of the
> > pad -- but there's nothing to sup
All areas -- more consistent feature set, menus, and shortcut keys across processes.
Some examples:
1) SP6 greatly enhanced the text editor, but someone forgot to update the shortcut
keys on the Edit menu -- they're still listing
the old Win3.x keys; fortunately the standard ones (Ctl+C,V,X,Z)
re split planes -- change PCB so that the plane layer must be the CURRENT
layer for the split to be editable. (How often do you edit the split,
compared to ALL the other parts on the board!)
I just did my first design that had one of these, and being CONSTANTLY
prompted to choose between the spl
Brian,
Have you seen/used component classes (or 'rooms')? They provide some of the facility
you're describing, although not as flexible.
The idea of having both preferred and disallowed areas for parts is interesting. To
make use of this additional information,
though, one would need an autopl
I'm new at this PCB stuff. We're just doing prototypes so far, and after getting my
3rd board back, I (finally) noticed that the
vias are not covered by solder mask. Looking at various PC cards and development kit
boards, I see that they usually are.
It looks like I can do this by setting a n
Two archives are available. Both are Eudora format, from Ian Wilson; one is from
11/1999 to 2/6/2000. It's available on
idrive.com -- see snips from 2 different posts below. The second is at
http://groups.yahoo.com/group/protel-users/files/, and
covers 1 May 2000 to 12 Aug 2000.
If it would
Andy,
I didn't notice anyone address the issue of why AC said the holes shorted, so I'll
take a shot. If you made the pads single-layer
(e.g., Top Layer) instead of MultiLayer, that's why. If you look at the PCB in
single-layer mode (Shift-S), for a single layer pad
there won't be 'negative co
Andy,
As far as why AC said the holes shorted, I'll take a guess: If you made the pads
single-layer (e.g., Top Layer) instead of
MultiLayer, that's why. If you look at the PCB in single-layer mode (Shift-S), for a
single layer pad there won't be 'negative
copper' on the inner planes to keep th
This problem appears to have just started happening with SP6: I have a single DDB,
with its window maximized. If I open enough
documents (sch, pcb, text, whatever) so that the document tabs along the top of the
window no longer fit, and scroll arrows appear,
then using the tabs becomes unrelia
Paul,
Two archives are available. Both are Eudora format, from Ian Wilson; one is from
11/1999 to 2/6/2000. It's available on
idrive.com -- see snips from 2 different posts below. The second is at
http://groups.yahoo.com/group/protel-users/files/, and
covers 1 May 2000 to 12 Aug 2000.
If it
Micky et al,
An important point here, that I just now realized: keepouts have NO EFFECT on planes!
Whether it's a keepout at the board edge, or
around a mounting hole, the gerbers do NOT get negative-copper in those areas. Which
is why everyone has to run these tracks around
the edges.
I onl
Alan,
Could this be put on the protel-users egroups/yahoo site? (URL:
http://groups.yahoo.com/group/protel-users/files ) In any case, I'd like a
copy. Let me know if you'd like me to put it on the above site.
Dwight Harm
[EMAIL PROTECTED]
> -Original Message-
> From:
I think you can either put no-ERC markers (the little red X's on the wiring toolbar)
on the inputs, or change the rule matrix.
-Original Message-
From: Rudolf Schaffer [mailto:[EMAIL PROTECTED]]
Sent: Saturday, March 10, 2001 3:44 AM
Hello,
When using Only Ports Global in a flat design
Go to http://groups.yahoo.com/group/protel-users/files/ and see protelfaq.html, which
is maintained by David Cary.
-Original Message-
From: Kim Lester [mailto:[EMAIL PROTECTED]]
Sent: Friday, March 09, 2001 8:19 PM
All,
I haven't seen a FAQ list around (please tell me if I miss
Is there a reason to prefer Vdd over GND? The spec sheets often just say
"tied high or low...", and my knowledge of theory is too weak to even guess
at an answer. :)
TIA,
Dwight Harm.
> -Original Message-
> From: Andy Gulliver [mailto:[EMAIL PROTECTED]]
> Sent: Wednes
I got tired of always having to uncheck the box, so I just leave them, but make them
hidden -- rt-click, Options, Show/Hide, Rooms.
BTW, the "Add component class" macros should have been in the Update Design list when
Mr. Robison synchronized -- I always review
the list to make sure it's doing
trial & error... I didn't try checking the manual. :)
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 06, 2001 3:58 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Update PCB from SCH bug?
Great answer - I think this might be one for the FAQ (what do you th
"Printed Circuit Board Basics", by Michael Flatt, has some interesting info, although
it's very manufacturing-oriented. You might
also try loading some of the Protel example files, and look at the PCB layouts in
single-layer mode (Shift-S toggles this in SP6).
The Protel help files also have so
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