Here is my reaction to Altium.
I am rather desperately hoping it is a hoax
Altium sounds like a name for a company that is trying to imitate
something modern without quite making it. It's very nineties.
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At 11:13 AM 8/24/01 -0500, Frank Gilley wrote:
Just curious, but lately I have been getting spammed from what would
appear to be email addy trawlers in this group.
Anyone else getting spam from .au's? after posting here?
This is not the usenet, surely we don't have to have addy trawlers in our
At 03:13 PM 12/5/2001 -0500, Brian Guralnick wrote:
Usually when I purchase any software, or hardware, from any other
vendor, I can
get support for free almost indefinitely without having to renew some sort of
membership.
Actually, indefinite support is, in my experience, the exception
At 03:51 PM 12/5/2001 -0500, Bagotronix Tech Support wrote:
I think that free support should be maintained for old products forever, as
long as there is no cost associated with maintaining that free support.
No cost support is possible. It consists of downloadable service packs
for the
At 06:05 PM 4/1/2002 +1000, Ian Wilson wrote:
Harmless unless you actually have unlocked the component - and then the
classic missing pad can be generated. Select a net (or connected copper),
which includes components with unlocked primitives. Delete the selection
and away go the pads. This
At 03:11 PM 4/1/2002 -0800, Dennis Saputelli wrote:
i am reasonable certain that my mysterious pad jump happened right after
and as a possible consequence of a File Save As
It would be rather surprising if that was not merely a coincidence. File
Save As does not have any effect on the file
At 12:43 AM 4/3/2002 +1000, Geoff Harland wrote:
I understand what you are saying, but I do wonder how much space you want
while you are moving items about; after all, 100 inches by 100 inches is a
pretty big area :) (i.e. much much larger than any PCB which I am ever
likely to be called upon to
At 01:08 PM 4/5/2002 +0100, [EMAIL PROTECTED] wrote:
Is there any way of excluding a component footprint from a DRC check?
You can set special rules for footprints, components, component classes, or
specific footprint pads, from some DRC checks, particularly Clearance
Constraint and a series
Unfortunately, single-layer mode has not be implemented in the best way.
It was apparently designed to be used for viewing, not really for editing.
The solution might be for Protel to disable selection entirely in
single-layer mode, or make single-layer mode edit the same as having the
same
At 11:49 AM 4/9/2002 +1000, Ian Wilson wrote:
Brad is correct - the original enquiry was not about archives but about the
servers and basic scripts. As Brad said, these are stored in the Files
store of the yahoo users group.
Not really important, yes, the original inquiry was about those
At 04:27 PM 4/8/2002 -0700, Shuping Lew wrote:
I try to add IC power table to Schematic...
Others gave good advice as to how to make a table in Schematic. So I'm
responding to the basic idea of making an IC power table.
It is essential, of course, that actual connections be made to power pins,
Sorry.
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At 03:23 PM 4/16/2002 -0700, Shuping Lew wrote:
I tried to load a netlist file to PCB. It has over 1,100 components. I
receiced a warning of access violation. It says: Access Violation at address
OF086CC6 module Exception Occurred in PCB: Netlist...
First of all, yes, I would strongly
At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote:
---I created netlist for each sheets. There are total 25 sheets. I then
loaded them individaully. There were no problem.
If the problem was, for example, that you had an incorrect scope such that
some net names were duplicated between sheets even
At 02:13 PM 4/17/2002 -0500, Robison Michael R CNIN wrote:
it was mentioned here a while ago that if i had hardcopy
artwork, i could scan it, get it sized appropriately, and
add it as a transparent background for me to use as a
guide for interactive routing. is this correct?
There are several
At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote:
I use some notes on every schematic project. So I created a schematic symbol
named note for it. To avoid the warning of missing footprint, I also
created a footprint named blank to associate with that symbol.
I think there is a better way. You can
At 05:33 PM 4/17/2002 -0500, Jon Elson wrote:
BUT, this applies ONLY to PCB, not schematic. ... I still don't know
of a way to do it
Tango Schematic can be read by Accel PCAD schematic (since that is the
descendant program) and PCAD schematic is convertible to Protel Schematic
through the
At 10:07 AM 4/18/2002 -0500, [EMAIL PROTECTED] wrote:
Is there anyway I can change the electrical type of a pin to one that is
not listed in the drop down menu? I would like to put an open drain on one
of the pins.
I rather doubt that there is a way. It would have to be in some kind of
system
If a translator cannot be found, it is not terribly difficult to massage
almost any netlist format into Protel form, unless the format is binary
instead of text. Sometimes one can use just a word processor, but if this
list is not organized by net, a spreadsheet like Excel can help with
At 09:52 PM 4/19/2002 -0400, Brian Guralnick wrote:
| I'll look into this, it may prevent the boot messages, etc. from spanning,
| though that is a minor annoyance.
|
It does.
Yes, it does, but it causes other problems. Six of one and a half dozen of
the other. No time to write about this
There is another problem with this rule If I am correct, it is indeed, a
hole clearance. But true clearance will be about 3 mils less, more or less,
because the holes are drilled oversize so that 1.5 mils of plating (1 oz)
will bring it back to the specified size. That is a conductive
At 11:30 AM 4/23/2002 -0700, JaMi Smith wrote:
Most of these boards are built in house, but the error rate on stuffing
components (the wrong ones in the wrong locations) is very high and the
trouble-shooting time to find these assembly errors is exhorbinate, so I
really do need the silkscreen
At 12:14 PM 4/24/2002 -0700, Afshin Salehi wrote:
Hello all,
Currently on PCB's I flood the top and bottom layers with a
ground plane after routing.
I've started doing that on certain boards, particularly fine-pitch SMT
boards. It can make a good 6-layer stackup, with power and
At 11:05 AM 4/25/2002 -0400, Jim Vegh wrote:
I have search all over the web and the previous forum posts and cannot
find bmptopcb anywhere.
There is a program which was donated to the user's group in the filespace
for [EMAIL PROTECTED]
At 02:58 PM 4/25/2002 +0100, Michael Binning wrote:
Dave, I have just tried creating a simple design using tracks in arc mode,
as a test.
Got to print preview OK, but as soon as I hit the print button, bye bye
Protel. Locked solid.
The problem may be file-specific, so it is crucial to save a
At 12:53 PM 4/30/2002 -0400, Bagotronix Tech Support wrote:
Since Protel DDBs are so huge now, fitting a large project on one CD-R might
be a problem.
Protel DDBs get large if one does not empty trash and compact the database.
The latter is the most important and the least visible problem, the
At 03:45 PM 4/30/2002 -0700, Mira wrote:
The meaning in Pcad is that you get all layers
swapped. Top goes to bottom, silk top - to silk
bottom. So it's like looking at the PCB from the
bottom side (or routing as the bottom side it your top
side).
There are three possible aspects to mirroring and
At 08:57 AM 5/1/2002 -0700, Tony Karavidas wrote:
No, PDF is a completely foreign file format. I don't imagine ANY EDA tool
reads PDF files and makes use of the 'information within.
Right. However, there may be a path to get some data in. Protel will import
DXF, and there are, I understand,
At 03:00 PM 5/1/2002 -0700, Mira wrote:
Does anybody know how expensive Phoenix will be?
I'm not sure that Altium even knows for sure. But they have announced that
pricing will be in line with current pricing, i.e., $7995 for 99SE full
regular price. There are often sales and specials for
I have been notified by a subscriber to this list that he received what is
probably a copy of one of the W32.Klez viruses, and that the mail appeared
to be from me.
This virus is known to spoof outgoing mail addresses, and it is quite
unlikely that I am infected -- though it is remotely
At 05:21 PM 5/1/2002 +, [EMAIL PROTECTED] wrote:
I am interested in purchasing Protel PCB/Schematic Software with license.
Prefer Protel 98 or newer.
For the information of our readers, older Protel licenses which have not
been used for upgrade are eligible for upgrade pricing. Right now,
At 05:49 PM 5/3/2002 +0200, Rene Tschaggelar wrote:
I have unassigned tracks (no net) and would like to proagate
the connected net.
In schematic there is a 'design/update pcb' that has a checkbox
for 'Assign net to connected copper'. That somewho does not appear
to work.
It should. It is
At 11:29 AM 5/3/2002 -0600, Cam Andruik wrote:
Well this is wierd. Yesterday Protel worked fine. Today I start it up and
it will not open a database. I have no Servers installed. If I add them,
the next time I start Protel they are all gone again!
Anyone ever seen this before?
Not this.
At 01:42 PM 5/4/2002 +0200, Rene Tschaggelar wrote:
Thank to all for these quick replies.
The netlist manager solved it. I didn't try to propagate
through unassigned vias, since they usually don't pick up the
changes in net assignment. So I did repeat {assign, place via}
until all nets were
At 10:06 AM 5/4/2002 +1000, Ian Wilson wrote:
On 01:03 PM 2/05/2002 -0400, Abd ulRahman Lomax said:
..snip..
I do understand that the Protel training, with Mr. Wilson, is quite good
Not me - I do not do any Protel training. Maybe some other Mr Wilson :-)
Ian Wilson
Yes, Rick Wilson
At 09:38 AM 5/7/2002 -0500, David VanHorn wrote:
Stop! Don't confuse the terms!
I'm not confused.
This has gotten a tad out of hand. The subject of this list is Protel
software, not RAID systems or whether person A or person B is or is not
confused. A RAID discussion is peripherally
At 02:00 AM 5/10/2002 -0700, Mira wrote:
Ian,
I use S-A and everything is selected. No hidden
layers.
Even though the strings on all layers could not be
deleted.
The strings are definitely selected and could be
moved.
E-D doesn't work. S-A selects everything. I checked
this on all layers. E-L
At 12:22 PM 5/13/2002 -0500, Jon Elson wrote:
If you do autoroute, you need to make the keep-out line out of straight
track segments. This is the only limitation I know of.
A hint for quickly and accurately making the outline out of arcs: draw an
arc of the right size and position, gerber
If gerber plots were not rounded off, there would be no problem with the
virtual shorts, and, in fact, if fab houses fabbed the boards as-is
without modifying the gerber, there would also be no problem.
But Protel does some rounding and it is not easy to exactly control
aperture assignments
in the (bad) case of using center origin and using gerber 2.3 i think
the
result was a 2 mil gap as the edges of the pads were pulled back toward
the center to the nearest mil
this notwithstanding it has proven to be a useful and clever tool
Dennis Saputelli
Abd ulRahman Lomax wrote:
If gerber
At 04:59 PM 5/15/2002 +1000, Thomas wrote:
I received an invite to apply for Protel DXP beta testing today.
As I have not signed it yet, I don't suppose its breaking the NDA to let you
know this.
It's my understanding that Beta testing was only being offered to those who
had already signed up
At 08:02 AM 5/15/2002 -0400, [EMAIL PROTECTED] wrote:
I received it yesterday. However, I haven't yet decided whether to sign or
not. Perhaps the biggest sticking point is that the license specifically
forbids me to use the beta to do real work - above and beyond the usual
disclaimers of
Due to a mail system error, this did not go out yesterday when it was written:
At 11:57 AM 5/14/2002 +0200, Georg Beckmann wrote:
For to do this, I use dummy parts usually 0402 resistors for the routing.
You have different nets for current and sense, you can also give them
different rules.
After
Due to a mail system error, this did not go out yesterday when it was written:
At 05:36 AM 5/14/2002 -0700, Fisher, Jerry wrote:
Did you run an ERC to see if the resistor is flagged with a connection
error.
This is absolutely the first thing that should be done; and the ERC matrix
should be
At 08:49 AM 5/15/2002 -0700, Brad Velander wrote:
[...]Another impact on revenue figures for this half is the re-scheduling
of our next major product release. Protel DXP, which is now expected
to go into external beta testing in May and released for sale in July
2002.
So I guess anybody can talk
At 11:26 AM 5/15/2002 -0700, Tony Karavidas wrote:
Rooms are great.
Yes, though their automatic generation can be a small nuisance.
The checkbox for adding rooms is the default setting, as I recall, so I'm
often getting rooms when I don't want them I'd prefer the default to be
settable or
At 01:37 PM 5/16/2002 -0700, Brad Velander wrote:
Abd ul-Rahman,
I agree with your general idea but suggest it is not practical with
a most designs.
Depends on how one tries to use it, doesn't it?
The text size would have to be so small as to make it
unreadable on anything but an E
At 08:16 AM 5/17/2002 -0700, [EMAIL PROTECTED] wrote:
4. It is good practice to provide fabricators with your whole design or at
least the .pcb file because often slight corrections are necessary to be
made just to adapt the pcb to their technologies, and let them generate
files and reports
At 11:08 AM 5/17/2002 -0700, Brad Velander wrote:
I developed my undying
adoration for Fab dwgs at one employer where we purchased our PCBs in
various shops usually located in China, Hong Kong, Singapore, India or
Korea. Try doing that without very complete and thorough Fab Dwgs. You (and
your
At 03:02 PM 5/19/2002 -0700, Embedded Matt wrote:
1. I placed an arc on the plane (my board is circular)
to form a circle all the way around the edge of the
board. The idea is to keep the plane away from the
edge of the board. The assigned net for the arc is
No Net. Is this the correct
At 02:35 PM 5/20/2002 +0500, Waheed Bajwa wrote:
Whats a polygon good for?
For filling an area of a PCB with copper. Also called a copper pour.
Properly set up, the inside of the polygon will fill with copper (track)
except for clearances as determined by the appropriate design rules around
At 10:36 AM 5/20/2002 -0700, Brooks,Bill wrote:
Okay, I'll jump in... The PCB fab house can do what ever it wants to make
the board.YOUR FAB DRAWING allows your company to ACCEPT/REJECT it if it
does not meet your standards.
Yes. Another reason not to specify as-drilled sizes. It is a lot
There is a free bmp to protel converter in the filespace for
[EMAIL PROTECTED] To access it, one must be registered with
yahoo as a member of the mailing list. There is another converter from a
designer in New Zealand: -- from a 1999 post by Harry Selfridge. I don't
know if Mr. Velthuizen is
At 12:16 PM 5/20/2002 -0700, Embedded Matt wrote:
Two easy ones (I think):
(1)
I have a multi-page schematic with ports to connect
nets between pages. Is there any way, besides adding
a net label, to force Protel to give the net the port
name in the netlist instead of something like R54_1?
If
At 11:03 AM 5/21/2002 -0400, Phillip Stevens wrote:
Is there a way to get cross project net names (net names from all
sheets in a project, not just the current schematic sheet) to
appear in the place net name dialog box pull down list?
Assuming that you have the panel displayed, with Browse
At 03:52 PM 5/21/2002 -0500, Robison Michael R CNIN wrote:
hi bruce,
oh! i used no name for them. and it went ahead and
netted everything together, even across different
packages and specific parts! i'll look into this.
maybe i can name them and lose the bad net.
I don't think so. Hidden
At 10:47 AM 5/23/2002 +0100, Ivor Davies wrote:
I have just joined this list and have my first query. We have a huge
number of PCB designs in Boardmaker (an old DOS package written by Tsien
of Cambridge, UK) and require to import them somehow into Protel.
BTW, there is a much newer version of
At 09:26 AM 5/23/2002 -0400, Jeff Adolphs wrote:
Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3
footprint has pins 1, 2, and two pin 3's. I thought this would work but
the pin 3's do not have netnames in the layout. Do I have to use a
schematic and footprint pin 3A and
At 11:14 AM 5/23/2002 -0700, Embedded Matt wrote:
I have placed a few pads on my PCB with the following
properties:
X size: 0
Y size: 0
Don't do that
Round
Hole size 147 mil
Multi-layer
Not plated
These are supposed to be mounting holes. I get
annular ring violations on these pads.
Of
Another solution, besides those already given, is to use, in the footprint,
through pads the size of vias and with the same hole size, given the same
net as the SM pad. You will have complete DRC protection
Another solution which might be better in some ways is to add a test point
(single
At 11:31 AM 5/23/2002 -0700, Brad Velander wrote:
Abd ul-Rahman or others,
do you know of a process using Protel V2.8 whereby you can read in
gerber type data with a unique name applied to pads or vias of certain
sizes.
No.
Then you can replace these uniquely named pads and via
At 04:29 PM 5/23/2002 -0400, you wrote:
I fixed the TO3 by assigning only one pad as pin 3. Will multiple pins
with one pin number work?
Yes. Fully with Schematic/Update PCB, and with a known bug which is
harmless once you know what it is with Netlist Load.
I have not had a problem with
At 06:19 AM 5/24/2002 -0700, Embedded Matt wrote:
Thanks for all the help on this question. I think the
best solution for me is to create a special rule for
these pads as some have suggested.
I also appreciate the information on non-plated holes.
Let me just add that the reason that I wanted a
At 02:03 PM 5/23/2002 -0700, Brad Velander wrote:
Abd ul-Rahman,
the naming is performed on the Gerber data (how I don't remember)
such that you have a pad flash with unique names for each different size
assignment. Then you can replace those assignments with a multilayer pad
globally. I
At 01:14 PM 5/29/2002 +1000, [EMAIL PROTECTED] wrote:
I just discovered another 'bug' fix for the spreadsheet editor. It always
seems
to default to locked and therefore any update you try to paste back from Excel
(a usable spreadsheet package) causes a crash and suggests a reboot.
That the
At 02:25 PM 5/24/2002 -0700, Brad Velander wrote:
Abd ul-Rahman,
no you are not describing the process that I was trying to recall.
Trust me, your description in no way resembles the process, nor is your
process limited to Ver. 2.8 is it?
No, it is not so limited. The process, as Mr.
At 11:07 PM 5/28/2002 -0600, John W. Childers wrote:
On a revision of a board, unwanted antennas can remain and must be found
and removed. These are tracks that branch out from a net, but don't
terminate on a pad, and can generate noise as electromagnetic waves, much
like an antenna on a
At 01:41 PM 5/31/2002 +0200, Shahab Sanjari wrote:
Sorry I was not at work due to an operation on my nose!
we won't ask any nosy questions.
But thank you all. As I stated, the problem occurs regardless
of type or footprint.
I will call this Remaining Netlisting Macros. Which means, after
At 11:45 AM 5/31/2002 -0700, Brad Velander wrote:
John,
my personal thoughts on the spreadsheet method was that it would
only work in the limited case where the track was only connected at one end.
In my past I have found a great deal of stubs where this method wouldn't
work because
At 10:57 AM 6/1/2002 -0500, David W. Gulley wrote:
I am doing some via-in-pad BGAs and need to figure out if there is a
good way to provide the top solder and top paste masks while keeping the
bottom solder mask and bottom paste masks off.
I defined the BGA pads as multilayer since I am doing
At 04:49 PM 6/4/2002 +0300, EDA Software Technical Dpt. wrote:
My PCB file contains Polygon Plane with 5 mils Clearance from the 18 mils
pads.
Ouch! 5 mils clearance from a plane is much more difficult to fab than 5
mils clearance between ordinary objects, because the plane clearance is
At 11:02 AM 6/4/2002 -0700, Bruce Walter wrote:
Anybody know if there would be a problem using a dash (minus sign) as a
prefix?
I think it works, but as another mentioned, WR will be sorted in a
different place than -WR.
Personally, I use an asterisk at the end, not because it is necessarily
At 09:31 PM 6/4/2002 -0400, Mitch Berkson wrote:
I'd like to draw graphical dashed lines in a schematic to indicate guard
traces which should be placed during PCB layout. Is there a way to do
this in Protel 99SE SP6?
Others have noted how to place a dashed line, and also that such a line has
At 11:18 AM 6/5/2002 -0600, Gordon Price wrote:
I decided to take a couple of layers and move them around from
the way they were and delete one of two ground plane layers( both named
GND). [...] I deleted one of the ground plane layers
and replaced it with a signal layer. I also moved the layers
At 10:19 AM 6/5/2002 -0400, Darryl Newberry wrote:
I switched my list prefs to DIGEST mode, but was annoyed to discover that
the digest is a hierarchy of attachments within attachments, to several
levels. This means I can't search by topic, and it's ridiculously time
consuming to find a
What does the Stack Manager show? What shows in the Design/Split Planes dialog?
At 10:10 AM 6/6/2002 +0200, [EMAIL PROTECTED] wrote:
I set up a board with 5 power planes; lateron I found out that by
efficiently using split planes I could reduce them to 4. The obsolete power
plane was named
At 11:24 AM 6/6/2002 +0200, Rene Tschaggelar wrote:
Complaining is one thing and acting another.
While I tend to think the ATS period of 2k$ to be a bit short
with one year, I also have to calculate what this investment
brings.
Note that the Protel web site now gives US$1495 as the value of the
At 06:05 AM 6/6/2002 -0700, Mira wrote:
I just tried to debugg a board, which schematic was in
Protel and the net names were RESET and RESET_. [...]
Due to the way the net labels are attached to the wire
in Protel, the underscore overlaps the wire and hardly
could be seen. That was what I meant.
At 12:10 PM 6/7/2002 -0400, Richard Sumner wrote:
You might simply add the mating connector pair to the schematic, and run
all required signals through both connectors. No net name changes needed.
Everything else is done in pcb layout. You end up with one board design
which is designed to
At 03:12 PM 6/7/2002 -0700, Brad Velander wrote:
Not to argue with you Abd ul-Rahman but Protel customer service has
specifically stated to me, a couple of times, with complete sincerity that
common CAD maintenance programs are typically 20% - 25% in the industry.
Cadence has been 15% for a long
At 05:26 PM 6/7/2002 -0400, [EMAIL PROTECTED] wrote:
I have just begun exploring the use of the Rooms feature, which is
tailor-made for a current board. I notice that the crosshatching which
indicates a room sometimes changes color, from a dark yellow to a dark red.
This is an on-line DRC
At 06:13 PM 6/7/2002 -0700, Dennis Saputelli wrote:
i've got a 144 pin PQFP 0.5mm pitch
there are only a small number of connected pins, maybe a dozen or so
excluding power
i am thinking about deleting a lot of unused pads to possibly open up
top side routes and reduce inspection and bridging
At 07:39 AM 6/10/2002 -0700, Robert Ritchey wrote:
This has probably been gone over before but I am just coming up to speed on
99SE. How can I set the default for the pad clearances and reliefs on the
inner
planes for split planes? Thanks,
Design/Rules/Manufacturing/Power Plane Clearance
At 11:15 AM 6/10/2002 -0700, Joey Nelson wrote:
The online help for matched net length rules seems to imply that if I set
a rule for a set of nets and then run Tools-Equalize Net Lengths, that
the shorter net will be accordioned to make up the difference, space
allowing. But this does not
At 06:35 AM 6/11/2002 -0700, Robert Ritchey wrote:
Hi,
Sorry, poorly worded question. How can I set the defaults so that when I
do a new PCB I always get what I want on these instead of 20mils as
seems to be the hard-coded default.
If you find out, let me know! By the way, I think the default
I've never seen anything like this. However, this is what I expect I would
do if I encountered this problem.
I would immediately take steps to move existing backups to a safe place,
where they cannot be subsequently overwritten. Backups exist in two places;
in the designated autobackup
At 10:06 AM 6/13/2002 -0400, Watnoski, Michael wrote:
When the Gerbers are generated without the 'Use Software Arcs' box
checked, parts of polygon copper pours become complete arcs where they
outline some pads. This is not a problem on the board design. These arcs
short to adjacent polygons and
At 01:22 PM 6/13/2002 -0400, Matt Daggett wrote:
Title: MDAC Drivers and ODBC Error Messages
Date: June 6, 2002
Keywords: ODBC, MDAC
Summary:Protel 99 SE uses the Microsoft MDAC drivers for the
implementation of the design database storage system. Some versions of the
MDAC
exists when 'Use Software Arcs' in not checked.
Michael Watnoski
Abd ulRahman Lomax wrote:
One thing he should try is to regenerate the Greber files at the highest
numeric resolution (2.5). Roundoff errors could cause the described
problem if the arcs were small. He doesn't mention whether
At 01:00 PM 6/14/2002 -0700, Dennis Saputelli wrote:
i can see the submil cracks in my defective virtual shorts quite easily
in CAMtastic
i would agree that it is a better tool for looking at gerbers than
protel
Just to note, Mr. Saputelli's problem with virtual shorts was due, as I
recall, to
As some of you know, I'm travelling this month to China; e-mail access may
be difficult for me, besides, I'll be occupied with
www.texturatrading.com/lucia.html
David Gulley [EMAIL PROTECTED] has moderator privileges on *all*
the Protel-users lists on yahoogroups.com (*not* this list on
At 02:49 PM 7/31/2002 -0400, Darryl Newberry wrote:
BTW, anybody going to join Altium's DXP list?
I have.
I bet the real reason they are
creating their own list is so THEY can filter and control the distribution.
I highly doubt it. Gad, what a paranoid view of the world! The yahoogroups
DXP
At 10:33 AM 7/31/2002 +0200, Gütlein, Ralf wrote:
As I recall, 'to bag' by word means 'to put sth. in a bag'.
In colloquial language this may stand for 'to snap' or 'to grab',
but in different countries there may be different flavors of
what it may mean. 'Abandon' makes also sense esp. if the bag
At 06:21 AM 7/31/2002 -0400, Frances Wheeler wrote:
Question to smartest of smartest designers out there:
She's too busy to read this list, so the rest of us will have to do.
Copper pours of this size are poured last because they are time
consuming. The pours can take 4 hours, and even longer
At 10:20 AM 8/29/2002 -0400, Narinder Kumar wrote:
Protel has no plan to run this new Protel DXP to run under Windows NT.
Not a good thing
Perhaps. Perhaps not. It is additional work, certainly, to make a program
function properly under multiple operating systems. Windows 2000 could be
The best way to learn is to make mistakes. To learn big, make big mistakes.
(Of course that isn't the whole story!)
At 12:29 PM 10/16/2002 -0700, JaMi Smith wrote:
Even if it is done at gerber time, it may make a difference in how Protel
defines the pad to the gerber file based upon whether it
At 10:26 PM 1/7/2004, Hamid A. Wasti wrote:
Abd ul-Rahman Lomax wrote:
In 99SE, this would be controlled by a Design Rule, and the choices for
scope are Board, Footprint, Component/Class, Net/Class, Pad Class and
Specification. I'm a little surprised not to see via there
Look harder. It is
At 08:00 PM 1/7/2004, you wrote:
In Protel DXP, SP2 - After generating gerber files I select fabrication
outputs - final to generate printed facsimiles of the gerber files. THE
DRILL SYMBOLS IN THE PRINT PREVIEW ARE DIFFERENT THAN THE GERBER FILES!!!
Irritating, I'm sure.
The same symbols
At 01:58 AM 1/8/2004, JaMi Smith wrote:
It would have been nice to be able to just select a single via,
as it appears that you can do with pads.
There are at least four ways, one of which you noted. As you mentioned, one
can create a via different in diameter or hole size (better the former),
At 01:58 AM 1/8/2004, JaMi Smith wrote:
... and while I too had never before investigateed the full list allowed by
the slider, right there at the bottom is what I am looking for
This is an example of why I consider it quite useful when I make a public
mistake. I'm not entirely dim, at least
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