At 03:03 PM 4/3/2002 +0100, Jason Morgan wrote:
>We have a board warping problem and are looking for a PCB expert to help
>resolve it.
>(Preferably located in the UK, but not important)
Unless it involves looking at the fabbed board itself -- we haven't gone
far enough to know if that would be
The yahoogroups lists have polling tools; in particular
[EMAIL PROTECTED], to which many of us are subscribed. This kind
of question, I think, would be better handled with a poll than with a
*very* anecdotal kind of "me too" or "me neither" thread on this list.
The polling feature on [EMAIL PR
ot* this list on Techserv) and
should be able to assist if needed.
If anyone needs to reach me personally, the best address to use is
[EMAIL PROTECTED] Lomax Design Associates mail ([EMAIL PROTECTED]) will
be reviewed by a colleague who can handle design and other client issues.
I plan to return b
nal
biases and animosities but rather a matter of consensus. But such steps are
rarely necessary. Most people, given clear and reasonable rules, can and
will follow them.)
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB de
ple who can do something about the problem as well as will be
those who are perceived as being friendly and supportive. However, even
open and declared enemies can often give us the most useful criticism, thus
Altium could be advised to listen well even to the most cantankerous
critics, but
s that must be clear, i.e., blown out, are highlighted and nothing
else, and the blowout layer is viewed on screen such that it obscures
anything underneath, any visible selection shows an error.)
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA licen
onded far more frequently on the DXP
list.
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
Easthampton, Massachusetts, USA
(413) 527-3881, efax (419) 730-4777
www.l
ring decision that is outside my realm. I'm told that it might be
important in some cases.
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
Easthampton, Massachusetts, USA
(413) 527-3881, efax (419) 730-4777
www.lomaxdesign.com
*
and all display is final, and no I am not in
single layer mode.
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
Easthampton, Massachusetts, USA
(413) 527-3881, efax (419) 730
then I can give no
general advice as to which to pour first But with polygon pours, it
might be better to split them so that pour is explicit. polygon pours with
the same net can overlap without any ambiguity. This is one way that
polygon pours are more flexible than inner planes. I think DXP f
At 03:13 PM 12/5/2001 -0500, Brian Guralnick wrote:
> Usually when I purchase any software, or hardware, from any other
> vendor, I can
>get support for free almost indefinitely without having to renew some sort of
>membership.
Actually, indefinite support is, in my experience, the exceptio
At 03:51 PM 12/5/2001 -0500, Bagotronix Tech Support wrote:
>I think that free support should be maintained for old products forever, as
>long as there is no cost associated with maintaining that free support.
>
>"No cost support" is possible. It consists of downloadable service packs
>for the so
At 06:05 PM 4/1/2002 +1000, Ian Wilson wrote:
Harmless unless you actually have unlocked the component - and then the
classic missing pad can be generated. Select a net (or connected copper),
which includes components with unlocked primitives. Delete the selection
and away go the pads. This
At 09:18 AM 4/1/2002 -0500, [EMAIL PROTECTED] wrote:
>Go to Tools, Preferences, and at the bottom center of the dialog box, turn
>off "Automatically Remove Loops".
This will indicate to Mr. Robison the cause of the behavior he saw. But if
he is doing cleanup, he should probably leave loop remova
At 04:37 PM 4/1/2002 -0500, Michael Reagan wrote:
>Kerry
>First you mentioned two types of objects, hanging traces, and dead tracks.
>To remove dead tracks
>
>1. Deselect all
>2. Select a dead track
>3 globally select all tracks matching layer and {NO NET)
>4. control delete to delete all at onc
At 03:11 PM 4/1/2002 -0800, Dennis Saputelli wrote:
>i am reasonable certain that my mysterious pad jump happened right after
>and as a possible consequence of a File Save As
It would be rather surprising if that was not merely a coincidence. File
Save As does not have any effect on the file its
At 12:43 AM 4/3/2002 +1000, Geoff Harland wrote:
>I understand what you are saying, but I do wonder how much space you want
>while you are moving items about; after all, 100 inches by 100 inches is a
>pretty big area :) (i.e. much much larger than any PCB which I am ever
>likely to be called upon
At 04:04 PM 4/3/2002 -0500, Lomax wrote:
>This list is also not the prime place to find advice on this, I'd suggest
>the IPC Designers Forum. Butyou never can tell...
Well, I did leave a door open I strongly suspect that the solution is
somewhere among all the suggestion
At 01:08 PM 4/5/2002 +0100, [EMAIL PROTECTED] wrote:
>Is there any way of excluding a component footprint from a DRC check?
You can set special rules for footprints, components, component classes, or
specific footprint pads, from some DRC checks, particularly Clearance
Constraint and a series o
At 10:29 AM 4/6/2002 -0800, [EMAIL PROTECTED] wrote:
>[...]In any case, does anybody have an early Windows based version that
>they would like to sell? Something close to the old 1.61 I had so I can
>at keep running without having to learn too much and without spending $4000.
Others have given
At 11:45 AM 4/8/2002 +0200, Schmitt Michael wrote:
>in the meantime i had deinstalled this server and reinstalled it again ...
>no chance.
Others have probably given effective advice on this, but just to be
complete, I'll note that the standard uninstall does not remove certain
configuration fi
Unfortunately, single-layer mode has not be implemented in the best way.
It was apparently designed to be used for viewing, not really for editing.
The solution might be for Protel to disable selection entirely in
single-layer mode, or make single-layer mode edit the same as having the
same la
At 08:23 AM 4/8/2002 -0700, Brad Velander wrote:
>Ted,
> they are in the "protel-users" group. You get access to them by
>clicking the "files" menu on the right hand side of the screen. Just checked
>and they are definitely there.
That is an older archive. There is a current archive kept
At 12:58 PM 4/8/2002 -0700, Brad Velander wrote:
> could you please explain your comments below. Where is this file
>area?
It isn't a file area. It is a message archive.
Try this:
http://groups.yahoo.com/group/protel-users-PEDA-Archive/messages
I think this is publicly accessible, you
At 11:49 AM 4/9/2002 +1000, Ian Wilson wrote:
Brad is correct - the original enquiry was not about archives but about the
servers and basic scripts. As Brad said, these are stored in the Files
store of the yahoo users group.
Not really important, yes, the original inquiry was about those files
At 04:27 PM 4/8/2002 -0700, Shuping Lew wrote:
>I try to add IC power table to Schematic...
Others gave good advice as to how to make a table in Schematic. So I'm
responding to the basic idea of making an "IC power table."
It is essential, of course, that actual connections be made to power pin
At 09:34 AM 4/9/2002 +0200, Edi Im Hof wrote:
I noticed this also. I just hit the spacebar fout times (rotate 360°) and
everything is fine. Clearly a bug.
Actually, a feature. Here is why this happens, I think:
Protel assumes, when you are placing parts, that you will want the relative
locatio
Sorry.
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At 09:10 AM 4/10/2002 -0700, Peter Bennett wrote:
>Sounds like a good theory...
>
>However, [...]
Normally, I try to thoroughly verify what I report. Sometimes, however, I
am unable to do that. Like now. So what I wrote should be treated as
nothing more than an unproven hypothesis. If I had tim
I've been having ISP problems. Verizon. Need I say more? Anyway, I think
they are fixed, courtesy of addr.com.
At 05:52 PM 4/11/2002 +0100, Jason Morgan wrote:
>As for the latest on the actual problem - board warping to well within IPC
>recomendations but outside of what we'd like, it seems that
At 11:53 AM 4/12/2002 -0700, JaMi Smith wrote:
>Interesting way of ascribing Intelligent Design to Sheer Oversight ...
No, it was merely a theory, as I wrote later, unverified. And indeed I
could not verify it, but perhaps only because I could not duplicate the
stray designator problem, even th
At 02:06 PM 4/12/2002 -0700, Embedded Matt wrote:
>Thanks to a tip from the FAQ for this mailing list, I
>got a copy of the BMP2PCB that I want to use to add my
>company logo to a PCB.
>
>I noticed that the tracks generated are 1 mil. Do
>board houses typically complain about these 1 mil
>tracks
At 05:08 PM 4/12/2002 -0400, Watnoski, Michael wrote:
> As long as they are a unique size, they can all be changed
>afterwards with a global selection.
I don't know, offhand, the answer to the original question, but I'd think
this answer would be less than fully satisfactory, because it
At 03:23 PM 4/16/2002 -0700, Shuping Lew wrote:
>I tried to load a netlist file to PCB. It has over 1,100 components. I
>receiced a warning of access violation. It says: Access Violation at address
>OF086CC6 module Exception Occurred in PCB: Netlist...
First of all, yes, I would strongly susp
At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote:
>---I created netlist for each sheets. There are total 25 sheets. I then
>loaded them individaully. There were no problem.
If the problem was, for example, that you had an incorrect scope such that
some net names were duplicated between sheets even
At 02:13 PM 4/17/2002 -0500, Robison Michael R CNIN wrote:
>it was mentioned here a while ago that if i had hardcopy
>artwork, i could scan it, get it sized appropriately, and
>add it as a transparent background for me to use as a
>guide for interactive routing. is this correct?
There are severa
At 12:40 AM 4/17/2002 +, [EMAIL PROTECTED] wrote:
>I am looking to import Tango(DOS) schematic and PCB files into Protel
>99SE. Is this supported by Protel ? If so, what's the process ?
Better to join the list and ask, then you'll know faster when you get an
answer, since you'll get it by
At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote:
>I use some notes on every schematic project. So I created a schematic symbol
>named "note" for it. To avoid the warning of missing footprint, I also
>created a footprint named "blank" to associate with that symbol.
I think there is a better way. Yo
At 05:33 PM 4/17/2002 -0500, Jon Elson wrote:
>BUT, this applies ONLY to PCB, not schematic. ... I still don't know
>of a way to do it
Tango Schematic can be read by Accel PCAD schematic (since that is the
descendant program) and PCAD schematic is convertible to Protel Schematic
through the PC
At 07:36 AM 4/18/2002 -0700, Graham wrote:
>At a recent Protel 99SE training session by Altium, I heard mention of
>the use of dual monitors in a single instance of Protel. Does anyone
>know how this is set up? It would be great to view two full-screen
>documents simultaneously. Thanks.
Windows
At 09:41 AM 4/18/2002 -0500, Robison Michael R CNIN wrote:
>thanks for responding. but i'm not exactly sure about
>what you mean when you say polygon planes don't connect
>to "other" nets. is the fill connecting to every thru-
>hole within its boundaries?
Yes. A "fill" is a bit misnamed. It is
At 10:07 AM 4/18/2002 -0500, [EMAIL PROTECTED] wrote:
> Is there anyway I can change the electrical type of a pin to one that is
>not listed in the drop down menu? I would like to put an open drain on one
>of the pins.
I rather doubt that there is a way. It would have to be in some kind of
syst
At 12:16 PM 4/18/2002 -0700, Dennis Saputelli wrote:
>we have 2 ea 21's and matrox G550 card
>can't get the center pop-up message dialogs to NOT straddle the screens
>
>what exactly did you do?
Matrox QuickDesk / Multi-Display Controls / Use Center POPUP / In Parent
Program Display.
I also have
At 08:33 AM 4/19/2002 -0500, Robison Michael R CNIN wrote:
>[...] the problem is that its a 10 layer board with very
>complex polygon pours, and everything must match closely
>with some legacy raster images of the layers. [...[
>management asked me if there was anything i could do to
>speed the j
At 10:30 PM 4/18/2002 -0400, Brian Guralnick wrote:
> When you install the matrox drivers, you must select 'Install
> enhanced multimonitor support'.
>Once in windows, in your advanced display control settings, for
>multimonitor mode, you muse select different resolution & # of
>colors foe e
At 03:32 PM 4/19/2002 -0500, Robison Michael R CNIN wrote:
>i'm going to come in this weekend and spend a little
>time working on a couple of the fancy pours and maybe
>experiment with mr. lomax's suggestions concerning two
>people splitting the work layer by layer.
Basically, both persons will b
designers generally don't have the resources, i.e., trusted
designers in other time zones, or other available designers in-house on
other shifts or free to work in parallel.
(3) we are just plain accustomed to working alone...
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consult
If a translator cannot be found, it is not terribly difficult to massage
almost any netlist format into Protel form, unless the format is binary
instead of text. Sometimes one can use just a word processor, but if this
list is not organized by net, a spreadsheet like Excel can help with
resort
At 03:26 PM 4/22/2002 -0400, [EMAIL PROTECTED] wrote:
>Hi all,
>I just tried to import a PADS ascii pcb and while some layers and fills
>showed up, only two components came across. I received the following errors
>in a report file
>-Load Errors : 1612
>-Expected number in line: 4518 at positio
At 09:52 PM 4/19/2002 -0400, Brian Guralnick wrote:
>| I'll look into this, it may prevent the boot messages, etc. from spanning,
>| though that is a minor annoyance.
>|
>It does.
Yes, it does, but it causes other problems. Six of one and a half dozen of
the other. No time to write about this to
There is another problem with this rule If I am correct, it is indeed, a
hole clearance. But true clearance will be about 3 mils less, more or less,
because the holes are drilled oversize so that 1.5 mils of plating (1 oz)
will bring it back to the specified size. That is a conductive reduction
At 02:11 PM 4/18/2002 -0500, Jon Elson wrote:
>Abd ulRahman Lomax wrote:
>
> > At 05:33 PM 4/17/2002 -0500, Jon Elson wrote:
> > >BUT, this applies ONLY to PCB, not schematic. ... I still don't know
> > >of a way to do it
> >
> > Tango Schematic can
At 09:16 AM 4/23/2002 +0100, Gareth Bradley wrote:
>Hi,
>I was wondering if it is possible to stop Protel placing vias under /any/
>components as the only method of manufacture I have is pin and hole
>vias. Protel places vias under P&H components (which I'm not /so/
>bothered about) but also u
At 11:30 AM 4/23/2002 -0700, JaMi Smith wrote:
>Most of these boards are built in house, but the error rate on stuffing
>components (the wrong ones in the wrong locations) is very high and the
>trouble-shooting time to find these assembly errors is exhorbinate, so I
>really do need the silkscreen
At 12:14 PM 4/24/2002 -0700, Afshin Salehi wrote:
>Hello all,
> Currently on PCB's I flood the top and bottom layers with a
> ground plane after routing.
I've started doing that on certain boards, particularly fine-pitch SMT
boards. It can make a good 6-layer stackup, with power and gro
At 11:05 AM 4/25/2002 -0400, Jim Vegh wrote:
>I have search all over the web and the previous forum posts and cannot
>find bmptopcb anywhere.
There is a program which was donated to the user's group in the filespace
for [EMAIL PROTECTED]
http://groups.yahoo.com/group/protel-users/files/Conve
At 02:58 PM 4/25/2002 +0100, Michael Binning wrote:
>Dave, I have just tried creating a simple design using tracks in arc mode,
>as a test.
>Got to print preview OK, but as soon as I hit the print button, bye bye
>Protel. Locked solid.
The problem may be file-specific, so it is crucial to save
The technique to automatically assign a net to a single pin has already
been given. (But note that if the "include single-pin nets" is not checked
next time net information is transferred, this will be lost.)
The behavior of the autorouter may not be as desired, however; of course
this only is
At 12:53 PM 4/30/2002 -0400, Bagotronix Tech Support wrote:
>Since Protel DDBs are so huge now, fitting a large project on one CD-R might
>be a problem.
Protel DDBs get large if one does not empty trash and compact the database.
The latter is the most important and the least visible problem, the
At 03:45 PM 4/30/2002 -0700, Mira wrote:
>The meaning in Pcad is that you get all layers
>swapped. Top goes to bottom, silk top - to silk
>bottom. So it's like looking at the PCB from the
>bottom side (or routing as the bottom side it your top
>side).
There are three possible aspects to "mirrorin
At 08:57 AM 5/1/2002 -0700, Tony Karavidas wrote:
>No, PDF is a completely foreign file format. I don't imagine ANY EDA tool
>reads PDF files and makes use of the 'information within.
Right. However, there may be a path to get some data in. Protel will import
DXF, and there are, I understand, so
At 03:00 PM 5/1/2002 -0700, Mira wrote:
>Does anybody know how expensive Phoenix will be?
I'm not sure that Altium even knows for sure. But they have announced that
pricing will be "in line with" current pricing, i.e., $7995 for 99SE full
regular price. There are often sales and specials for mu
I have been notified by a subscriber to this list that he received what is
probably a copy of one of the W32.Klez viruses, and that the mail appeared
to be from me.
This virus is known to spoof outgoing mail addresses, and it is quite
unlikely that I am infected -- though it is remotely possib
At 05:21 PM 5/1/2002 +, [EMAIL PROTECTED] wrote:
>I am interested in purchasing Protel PCB/Schematic Software with license.
>Prefer Protel 98 or newer.
For the information of our readers, older Protel licenses which have not
been used for upgrade are eligible for upgrade pricing. Right now,
n the supplied libraries.
A mailing list was started to deal with the issues involved in organizing a
user library; like most of the accessory lists, it has had very little
activity, but it is there for use; to join send a piece of mail to
[EMAIL PROTECTED]
Abd ulRahman Lomax
Chair, Protel
At 05:49 PM 5/3/2002 +0200, Rene Tschaggelar wrote:
>I have unassigned tracks (no net) and would like to proagate
>the connected net.
>In schematic there is a 'design/update pcb' that has a checkbox
>for 'Assign net to connected copper'. That somewho does not appear
>to work.
It should. It is pos
At 11:29 AM 5/3/2002 -0600, Cam Andruik wrote:
>Well this is wierd. Yesterday Protel worked fine. Today I start it up and
>it will not open a database. I have no Servers installed. If I add them,
>the next time I start Protel they are all gone again!
>
>Anyone ever seen this before?
Not this.
At 01:42 PM 5/4/2002 +0200, Rene Tschaggelar wrote:
>Thank to all for these quick replies.
>The netlist manager solved it. I didn't try to propagate
>through unassigned vias, since they usually don't pick up the
>changes in net assignment. So I did repeat {assign, place via}
>until all nets were c
At 10:06 AM 5/4/2002 +1000, Ian Wilson wrote:
>On 01:03 PM 2/05/2002 -0400, Abd ulRahman Lomax said:
><..snip..>
>>I do understand that the Protel training, with Mr. Wilson, is quite good
>
>Not me - I do not do any Protel training. Maybe some other Mr Wilson :-
At 09:38 AM 5/7/2002 -0500, David VanHorn wrote:
>>Stop! Don't confuse the terms!
>
>I'm not confused.
This has gotten a tad out of hand. The subject of this list is Protel
software, not RAID systems or whether person A or person B is or is not
confused. A RAID discussion is peripherally rela
At 02:00 AM 5/10/2002 -0700, Mira wrote:
>Ian,
>
>I use S-A and everything is selected. No hidden
>layers.
>Even though the strings on all layers could not be
>deleted.
>The strings are definitely selected and could be
>moved.
>E-D doesn't work. S-A selects everything. I checked
>this on all layer
At 12:22 PM 5/13/2002 -0500, Jon Elson wrote:
>If you do autoroute, you need to make the keep-out line out of straight
>track segments. This is the only limitation I know of.
A hint for quickly and accurately making the outline out of arcs: draw an
arc of the right size and position, gerber pho
If gerber plots were not rounded off, there would be no problem with the
"virtual shorts," and, in fact, if fab houses fabbed the boards as-is
without modifying the gerber, there would also be no problem.
But Protel does some rounding and it is not easy to exactly control
aperture assignments
>even in gerber 2.4
>my gap was i think .005 mil
>
>in the (bad) case of using center origin and using gerber 2.3 i think
>the
>result was a 2 mil gap as the edges of the pads were pulled back toward
>the center to the nearest mil
>
>this notwithstanding it has proven to be a
At 04:59 PM 5/15/2002 +1000, Thomas wrote:
>I received an invite to apply for Protel DXP beta testing today.
>As I have not signed it yet, I don't suppose its breaking the NDA to let you
>know this.
It's my understanding that Beta testing was only being offered to those who
had already signed up
At 08:02 AM 5/15/2002 -0400, [EMAIL PROTECTED] wrote:
>I received it yesterday. However, I haven't yet decided whether to sign or
>not. Perhaps the biggest sticking point is that the license specifically
>forbids me to use the beta to do real work - above and beyond the usual
>disclaimers of liabi
PROTECTED] wrote:
>This sounds like a perfect application for the "Lomax virtual short" which
>has been discussed on this board. Check the archives for details, but in a
>nutshell you create a part which has a gap which is too small to fabricate
>(i.e. 0.02"), an
Due to a mail system error, this did not go out yesterday when it was written:
At 05:36 AM 5/14/2002 -0700, Fisher, Jerry wrote:
>Did you run an ERC to see if the resistor is flagged with a connection
>error.
This is absolutely the first thing that should be done; and the ERC matrix
should be
At 08:49 AM 5/15/2002 -0700, Brad Velander wrote:
>[...]"Another impact on revenue figures for this half is the re-scheduling
>of our next major product release. Protel DXP, which is now expected
>to go into external beta testing in May and released for sale in July
>2002."
>
>So I guess anybody c
At 11:26 AM 5/15/2002 -0700, Tony Karavidas wrote:
>Rooms are great.
Yes, though their automatic generation can be a small nuisance.
The checkbox for adding rooms is the default setting, as I recall, so I'm
often getting rooms when I don't want them I'd prefer the default to be
settable or
At 11:31 AM 5/16/2002 -0700, Brad Velander wrote:
> The KB 1472 is so nice, they don't even suggest that letter
>characters might solve the problem so you are left to wonder. Is there a
>limit of 16 sizes even with the letter symbols?
Actually, in my opinion, the best practice is to use
At 01:37 PM 5/16/2002 -0700, Brad Velander wrote:
>Abd ul-Rahman,
> I agree with your general idea but suggest it is not practical with
>a most designs.
Depends on how one tries to use it, doesn't it?
> The text size would have to be so small as to make it
>unreadable on anything but an
Anomalies found by the
fabricator should always be queried to the designer even if they seem easy
to fix. One person's anomaly can be another person's special design condition.
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
East
At 11:08 AM 5/17/2002 -0700, Brad Velander wrote:
>I developed my undying
>adoration for Fab dwgs at one employer where we purchased our PCBs in
>various shops usually located in China, Hong Kong, Singapore, India or
>Korea. Try doing that without very complete and thorough Fab Dwgs. You (and
>you
At 03:02 PM 5/19/2002 -0700, Embedded Matt wrote:
>1. I placed an arc on the plane (my board is circular)
>to form a circle all the way around the edge of the
>board. The idea is to keep the plane away from the
>edge of the board. The assigned net for the arc is
>"No Net". Is this the correct p
At 02:35 PM 5/20/2002 +0500, Waheed Bajwa wrote:
>Whats a polygon good for?
For filling an area of a PCB with copper. Also called a "copper pour."
Properly set up, the inside of the polygon will fill with copper (track)
except for clearances as determined by the appropriate design rules around
At 10:36 AM 5/20/2002 -0700, Brooks,Bill wrote:
>Okay, I'll jump in... The PCB fab house can do what ever it wants to make
>the board.YOUR FAB DRAWING allows your company to ACCEPT/REJECT it if it
>does not meet your standards.
Yes. Another reason not to specify as-drilled sizes. It is a lot
There is a free bmp to protel converter in the filespace for
[EMAIL PROTECTED] To access it, one must be registered with
yahoo as a member of the mailing list. There is another converter from a
designer in New Zealand: -- from a 1999 post by Harry Selfridge. I don't
know if Mr. Velthuizen is s
At 12:16 PM 5/20/2002 -0700, Embedded Matt wrote:
>Two easy ones (I think):
>
>(1)
>I have a multi-page schematic with ports to connect
>nets between pages. Is there any way, besides adding
>a net label, to force Protel to give the net the port
>name in the netlist instead of something like R54_1
At 11:03 AM 5/21/2002 -0400, Phillip Stevens wrote:
>Is there a way to get cross project net names (net names from all
>sheets in a project, not just the current schematic sheet) to
>appear in the place net name dialog box pull down list?
Assuming that you have the panel displayed, with Browse
At 03:52 PM 5/21/2002 -0500, Robison Michael R CNIN wrote:
>hi bruce,
>
>oh! i used no name for them. and it went ahead and
>netted everything together, even across different
>packages and specific parts! i'll look into this.
>maybe i can name them and lose the bad net.
I don't think so. Hidde
At 10:47 AM 5/23/2002 +0100, Ivor Davies wrote:
>I have just joined this list and have my first query. We have a huge
>number of PCB designs in Boardmaker (an old DOS package written by Tsien
>of Cambridge, UK) and require to import them somehow into Protel.
BTW, there is a much newer version o
At 09:26 AM 5/23/2002 -0400, Jeff Adolphs wrote:
>Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3
>footprint has pins 1, 2, and two pin 3's. I thought this would work but
>the pin 3's do not have netnames in the layout. Do I have to use a
>schematic and footprint pin 3A and
At 11:14 AM 5/23/2002 -0700, Embedded Matt wrote:
>I have placed a few pads on my PCB with the following
>properties:
>
>X size: 0
>Y size: 0
Don't do that
>Round
>Hole size 147 mil
>Multi-layer
>Not plated
>
>These are supposed to be mounting holes. I get
>annular ring violations on these
Another solution, besides those already given, is to use, in the footprint,
through pads the size of vias and with the same hole size, given the same
net as the SM pad. You will have complete DRC protection
Another solution which might be better in some ways is to add a test point
(single
At 11:31 AM 5/23/2002 -0700, Brad Velander wrote:
>Abd ul-Rahman or others,
> do you know of a process using Protel V2.8 whereby you can read in
>gerber type data with a unique name applied to pads or vias of certain
>sizes.
No.
> Then you can replace these uniquely named pads and via f
At 04:29 PM 5/23/2002 -0400, you wrote:
>I fixed the TO3 by assigning only one pad as pin 3. Will multiple pins
>with one pin number work?
Yes. Fully with Schematic/Update PCB, and with a known bug which is
harmless once you know what it is with Netlist Load.
>I have not had a problem with Net
At 06:19 AM 5/24/2002 -0700, Embedded Matt wrote:
>Thanks for all the help on this question. I think the
>best solution for me is to create a special rule for
>these pads as some have suggested.
>
>I also appreciate the information on non-plated holes.
>
>Let me just add that the reason that I wa
At 02:03 PM 5/23/2002 -0700, Brad Velander wrote:
>Abd ul-Rahman,
> the naming is performed on the Gerber data (how I don't remember)
>such that you have a pad flash with unique names for each different size
>assignment. Then you can replace those assignments with a multilayer pad
>globall
At 01:14 PM 5/29/2002 +1000, [EMAIL PROTECTED] wrote:
>I just discovered another 'bug' fix for the spreadsheet editor. It always
>seems
>to default to locked and therefore any update you try to paste back from Excel
>(a usable spreadsheet package) causes a crash and suggests a reboot.
That the
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